2016-07-19 16:58:37 +00:00
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From: Matthias Schiffer <mschiffer@universe-factory.net>
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Date: Tue, 19 Jul 2016 17:48:53 +0200
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Subject: ar71xx: define wmac reset function for QCA955x
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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Backport of LEDE a176168a85477caa44eef7e979567d1d52868fde
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diff --git a/target/linux/ar71xx/patches-3.18/640-MIPS-ath79-add-QCA955x-wmac-reset.patch b/target/linux/ar71xx/patches-3.18/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
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new file mode 100644
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2016-12-20 00:09:53 +00:00
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index 0000000000000000000000000000000000000000..4ac5acd618748fc9ad0f091d110d2503cdc39d53
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2016-07-19 16:58:37 +00:00
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--- /dev/null
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+++ b/target/linux/ar71xx/patches-3.18/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
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@@ -0,0 +1,71 @@
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+--- a/arch/mips/ath79/common.h
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++++ b/arch/mips/ath79/common.h
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+@@ -19,6 +19,8 @@
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+ #define ATH79_MEM_SIZE_MIN (2 * 1024 * 1024)
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+ #define ATH79_MEM_SIZE_MAX (128 * 1024 * 1024)
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+
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++extern void __iomem *ath79_ddr_base;
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++
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+ void ath79_clocks_init(void);
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+ unsigned long ath79_get_sys_clk_rate(const char *id);
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+
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+--- a/arch/mips/ath79/dev-wmac.c
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++++ b/arch/mips/ath79/dev-wmac.c
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+@@ -149,6 +149,27 @@ static void ar934x_wmac_setup(void)
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+ ath79_wmac_data.is_clk_25mhz = true;
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+ }
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+
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++static int ar955x_wmac_reset(void)
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++{
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++ int i;
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++
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++ /* Try to wait for WMAC DDR activity to stop */
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++ for (i = 0; i < 10; i++) {
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++ if (!(__raw_readl(ath79_ddr_base + QCA955X_DDR_CTL_CONFIG) &
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++ QCA955X_DDR_CTL_CONFIG_ACT_WMAC))
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++ break;
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++
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++ udelay(10);
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++ }
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++
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++ ath79_device_reset_set(QCA955X_RESET_RTC);
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++ udelay(10);
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++ ath79_device_reset_clear(QCA955X_RESET_RTC);
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++ udelay(10);
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++
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++ return 0;
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++}
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++
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+ static void qca955x_wmac_setup(void)
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+ {
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+ u32 t;
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+@@ -165,6 +186,8 @@ static void qca955x_wmac_setup(void)
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+ ath79_wmac_data.is_clk_25mhz = false;
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+ else
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+ ath79_wmac_data.is_clk_25mhz = true;
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++
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++ ath79_wmac_data.external_reset = ar955x_wmac_reset;
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+ }
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+
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+ static bool __init
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+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+@@ -32,7 +32,7 @@
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+ #define AR71XX_SPI_SIZE 0x01000000
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+
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+ #define AR71XX_DDR_CTRL_BASE (AR71XX_APB_BASE + 0x00000000)
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+-#define AR71XX_DDR_CTRL_SIZE 0x100
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++#define AR71XX_DDR_CTRL_SIZE 0x200
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+ #define AR71XX_UART_BASE (AR71XX_APB_BASE + 0x00020000)
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+ #define AR71XX_UART_SIZE 0x100
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+ #define AR71XX_USB_CTRL_BASE (AR71XX_APB_BASE + 0x00030000)
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+@@ -173,6 +173,9 @@
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+ #define AR934X_DDR_REG_FLUSH_PCIE 0xa8
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+ #define AR934X_DDR_REG_FLUSH_WMAC 0xac
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+
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++#define QCA955X_DDR_CTL_CONFIG 0x108
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++#define QCA955X_DDR_CTL_CONFIG_ACT_WMAC BIT(23)
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++
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+ /*
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+ * PLL block
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+ */
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