48 lines
1.8 KiB
Diff
48 lines
1.8 KiB
Diff
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From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
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Date: Wed, 16 Mar 2016 09:27:01 +0000
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Subject: ar71xx: Extend the list of bits in QCA955X_GMAC_REG_ETH_CFG
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Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
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Backport of r49027
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Forwarded: https://patchwork.ozlabs.org/patch/624180/
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diff --git a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
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index 8bf7658..797977f 100644
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--- a/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
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+++ b/target/linux/ar71xx/patches-3.18/601-MIPS-ath79-add-more-register-defines.patch
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@@ -207,7 +207,7 @@
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#define AR934X_GPIO_REG_FUNC 0x6c
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#define AR71XX_GPIO_COUNT 16
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-@@ -560,4 +663,153 @@
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+@@ -560,4 +663,170 @@
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#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
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#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
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@@ -358,6 +358,23 @@
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+#define QCA955X_GMAC_REG_ETH_CFG 0x00
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+
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+#define QCA955X_ETH_CFG_RGMII_EN BIT(0)
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++#define QCA955X_ETH_CFG_MII_GE0 BIT(1)
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++#define QCA955X_ETH_CFG_GMII_GE0 BIT(2)
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++#define QCA955X_ETH_CFG_MII_GE0_MASTER BIT(3)
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++#define QCA955X_ETH_CFG_MII_GE0_SLAVE BIT(4)
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++#define QCA955X_ETH_CFG_GE0_ERR_EN BIT(5)
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+#define QCA955X_ETH_CFG_GE0_SGMII BIT(6)
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++#define QCA955X_ETH_CFG_RMII_GE0 BIT(10)
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++#define QCA955X_ETH_CFG_MII_CNTL_SPEED BIT(11)
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++#define QCA955X_ETH_CFG_RMII_GE0_MASTER BIT(12)
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++#define QCA955X_ETH_CFG_RXD_DELAY_MASK 0x3
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++#define QCA955X_ETH_CFG_RXD_DELAY_SHIFT 14
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++#define QCA955X_ETH_CFG_RDV_DELAY BIT(16)
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++#define QCA955X_ETH_CFG_RDV_DELAY_MASK 0x3
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++#define QCA955X_ETH_CFG_RDV_DELAY_SHIFT 16
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++#define QCA955X_ETH_CFG_TXD_DELAY_MASK 0x3
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++#define QCA955X_ETH_CFG_TXD_DELAY_SHIFT 18
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++#define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
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++#define QCA955X_ETH_CFG_TXE_DELAY_SHIFT 20
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+
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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