79 lines
2.5 KiB
Diff
79 lines
2.5 KiB
Diff
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From: Sven Eckelmann <sven.eckelmann@open-mesh.com>
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Date: Wed, 16 Mar 2016 09:27:11 +0000
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Subject: ar71xx: Use PHY fixups for Open Mesh MR900
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The delays of PHY/MAC on the MR900 are done by u-boot and OpenWrt in
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different ways. u-boot only modifies the ETH_CFG of the QCA955x based on
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the link speed. But OpenWrt can only modify the PHY delays based on the
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link speed.
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This can lead to communication problems when u-boot initializes the ETH_CFG
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for a specific link speed (e.g. 10BASE-T) but then OpenWrt the sets the PHY
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delays to an incompatible value.
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Instead reset the ETH_CFG delay bits of the QCA955x to a specific value and
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only rely on the AT803x PHY settings.
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Signed-off-by: Sven Eckelmann <sven.eckelmann@open-mesh.com>
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Backport of r49030
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Forwarded: https://patchwork.ozlabs.org/patch/624185/
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diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
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index 9c3164d..3634bf0 100644
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--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
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+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-mr900.c
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@@ -23,6 +23,7 @@
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#include <linux/ath9k_platform.h>
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#include <asm/mach-ath79/ar71xx_regs.h>
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+#include <linux/platform_data/phy-at803x.h>
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#include "common.h"
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#include "dev-ap9x-pci.h"
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@@ -94,15 +95,30 @@ static struct gpio_keys_button mr900_gpio_keys[] __initdata = {
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},
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};
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+static struct at803x_platform_data mr900_at803x_data = {
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+ .disable_smarteee = 1,
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+ .enable_rgmii_rx_delay = 1,
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+ .enable_rgmii_tx_delay = 0,
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+ .fixup_rgmii_tx_delay = 1,
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+};
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+
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+static struct mdio_board_info mr900_mdio0_info[] = {
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+ {
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+ .bus_id = "ag71xx-mdio.0",
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+ .phy_addr = 5,
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+ .platform_data = &mr900_at803x_data,
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+ },
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+};
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+
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static void __init mr900_setup(void)
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{
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u8 *art = (u8 *)KSEG1ADDR(0x1fff0000);
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u8 mac[6], pcie_mac[6];
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struct ath9k_platform_data *pdata;
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- ath79_eth0_pll_data.pll_1000 = 0xbe000101;
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- ath79_eth0_pll_data.pll_100 = 0x80000101;
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- ath79_eth0_pll_data.pll_10 = 0x80001313;
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+ ath79_eth0_pll_data.pll_1000 = 0xae000000;
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+ ath79_eth0_pll_data.pll_100 = 0xa0000101;
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+ ath79_eth0_pll_data.pll_10 = 0xa0001313;
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ath79_register_m25p80(NULL);
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@@ -126,6 +142,9 @@ static void __init mr900_setup(void)
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ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
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ath79_register_mdio(0, 0x0);
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+ mdiobus_register_board_info(mr900_mdio0_info,
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+ ARRAY_SIZE(mr900_mdio0_info));
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+
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ath79_init_mac(ath79_eth0_data.mac_addr, art + MR900_MAC0_OFFSET, 0);
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/* GMAC0 is connected to the RMGII interface */
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