45 lines
2.3 KiB
Diff
45 lines
2.3 KiB
Diff
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From: Roger Pueyo Centelles <roger.pueyo@guifi.net>
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Date: Mon, 24 Dec 2018 15:39:32 +0100
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Subject: kernel: mtd: add support for EN25QH64 in spi-nor.c
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The Eon EN25QH64 is a 64 Mbit SPI NOR flash memory chip. Its 32, 128 and
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256 Mbits siblings are supported upstream but this particular size wasn't.
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This commit includes patches for kernels 4.14 and 4.19.
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Tested on a COMFAST CF-E120A v3 (ath79).
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Signed-off-by: Roger Pueyo Centelles <roger.pueyo@guifi.net>
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diff --git a/target/linux/generic/pending-4.14/479-mtd-spi-nor-add-eon-en25qh64.patch b/target/linux/generic/pending-4.14/479-mtd-spi-nor-add-eon-en25qh64.patch
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new file mode 100644
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index 0000000000000000000000000000000000000000..c290a784d045576b6f145d489ed4580477ee7829
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--- /dev/null
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+++ b/target/linux/generic/pending-4.14/479-mtd-spi-nor-add-eon-en25qh64.patch
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@@ -0,0 +1,10 @@
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+--- a/drivers/mtd/spi-nor/spi-nor.c
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++++ b/drivers/mtd/spi-nor/spi-nor.c
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+@@ -956,6 +956,7 @@ static const struct flash_info spi_nor_i
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+ { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
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+ { "en25q128", INFO(0x1c3018, 0, 64 * 1024, 256, SECT_4K) },
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+ { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
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++ { "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128, 0) },
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+ { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
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+ { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
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+ { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
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diff --git a/target/linux/generic/pending-4.19/479-mtd-spi-nor-add-eon-en25qh64.patch b/target/linux/generic/pending-4.19/479-mtd-spi-nor-add-eon-en25qh64.patch
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new file mode 100644
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index 0000000000000000000000000000000000000000..6bb77547332d6d9dc2944f45edc5d170fdfdc7aa
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--- /dev/null
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+++ b/target/linux/generic/pending-4.19/479-mtd-spi-nor-add-eon-en25qh64.patch
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@@ -0,0 +1,10 @@
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+--- a/drivers/mtd/spi-nor/spi-nor.c
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++++ b/drivers/mtd/spi-nor/spi-nor.c
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+@@ -996,6 +996,7 @@ static const struct flash_info spi_nor_i
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+ { "en25q64", INFO(0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
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+ { "en25q128", INFO(0x1c3018, 0, 64 * 1024, 256, SECT_4K) },
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+ { "en25qh32", INFO(0x1c7016, 0, 64 * 1024, 64, 0) },
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++ { "en25qh64", INFO(0x1c7017, 0, 64 * 1024, 128, 0) },
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+ { "en25qh128", INFO(0x1c7018, 0, 64 * 1024, 256, 0) },
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+ { "en25qh256", INFO(0x1c7019, 0, 64 * 1024, 512, 0) },
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+ { "en25s64", INFO(0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
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