183 lines
7.5 KiB
Diff
183 lines
7.5 KiB
Diff
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From: Sven Eckelmann <sven@narfation.org>
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Date: Fri, 19 Jan 2018 14:02:09 +0100
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Subject: ar71xx: disable 40Mhz refclk for QCA953x
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The "QCA9531 v2.0 802.11n 2x2 2.4 GHz Premium SOC for WLAN Platforms"
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datasheet (80-Y7991-1 Rev. C - October 2014) doesn't specify support for a
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40 Mhz reference clock. The register description for "Bootstrap Options"
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(page 31) defines following states for the bit 4 (REF_CLK):
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* 0 - CLK25 (default)
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* 1 - (reserved)
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Devices like the TP-Link CPE210 v2 has this bit set to 1 but is using a 25
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Mhz reference clock. OpenWrt is still interpreted this bit as 40 Mhz and
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then break the bootup of the system due to this incorrect interpretation.
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Signed-off-by: Sven Eckelmann <sven@narfation.org>
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[refreshed patches]
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Signed-off-by: Piotr Dymacz <pepe2k@gmail.com>
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Origin: backport, https://github.com/openwrt/openwrt/commit/b1d57dadb2da0e010e157fd2383523578c9dcc2e
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diff --git a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
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index 777f7b2c8838f2c93f79d5d5212f90b2bd82ced3..d55c97165a5abad8cb25fcc6ddc29415f238c7e6 100644
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--- a/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
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+++ b/target/linux/ar71xx/patches-4.4/620-MIPS-ath79-add-support-for-QCA953x-SoC.patch
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@@ -44,7 +44,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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config ATH79_NVRAM
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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-@@ -354,6 +354,91 @@ static void __init ar934x_clocks_init(vo
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+@@ -354,6 +354,87 @@ static void __init ar934x_clocks_init(vo
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iounmap(dpll_base);
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}
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@@ -56,13 +56,9 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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+ unsigned long ahb_rate;
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+ u32 cpu_pll, ddr_pll;
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-+ u32 bootstrap;
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+
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-+ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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-+ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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-+ ref_rate = 40 * 1000 * 1000;
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-+ else
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-+ ref_rate = 25 * 1000 * 1000;
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++ /* QCA953X only supports 25MHz ref_clk */
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++ ref_rate = 25 * 1000 * 1000;
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+
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+ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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+ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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@@ -136,7 +132,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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static void __init qca955x_clocks_init(void)
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{
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unsigned long ref_rate;
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-@@ -451,6 +536,8 @@ void __init ath79_clocks_init(void)
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+@@ -451,6 +532,8 @@ void __init ath79_clocks_init(void)
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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@@ -247,14 +243,12 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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ath79_wmac_data.external_reset = ar933x_wmac_reset;
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}
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-@@ -151,6 +151,26 @@ static void ar934x_wmac_setup(void)
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+@@ -151,6 +151,21 @@ static void ar934x_wmac_setup(void)
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ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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}
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+static void qca953x_wmac_setup(void)
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+{
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-+ u32 t;
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-+
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+ ath79_wmac_device.name = "qca953x_wmac";
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+
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+ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
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@@ -262,11 +256,8 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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+ ath79_wmac_resources[1].start = ATH79_IP2_IRQ(1);
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+ ath79_wmac_resources[1].end = ATH79_IP2_IRQ(1);
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+
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-+ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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-+ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
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-+ ath79_wmac_data.is_clk_25mhz = false;
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-+ else
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-+ ath79_wmac_data.is_clk_25mhz = true;
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++ /* QCA953X only supports 25MHz ref_clk */
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++ ath79_wmac_data.is_clk_25mhz = true;
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+
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+ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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+}
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@@ -274,7 +265,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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static void qca955x_wmac_setup(void)
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{
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u32 t;
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-@@ -368,6 +388,8 @@ void __init ath79_register_wmac(u8 *cal_
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+@@ -368,6 +383,8 @@ void __init ath79_register_wmac(u8 *cal_
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ar933x_wmac_setup();
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else if (soc_is_ar934x())
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ar934x_wmac_setup();
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@@ -550,7 +541,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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+#define QCA953X_BOOTSTRAP_SW_OPTION2 BIT(12)
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+#define QCA953X_BOOTSTRAP_SW_OPTION1 BIT(11)
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+#define QCA953X_BOOTSTRAP_EJTAG_MODE BIT(5)
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-+#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
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++#define QCA953X_BOOTSTRAP_REF_CLK BIT(4)
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+#define QCA953X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
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+#define QCA953X_BOOTSTRAP_DDR1 BIT(0)
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+
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diff --git a/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch b/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
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index ed90c40d882fcff1a451533748912865cc78c6e8..de0ee4604cdeb946bab222cacaa51fb150b25aab 100644
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--- a/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
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+++ b/target/linux/ar71xx/patches-4.4/621-MIPS-ath79-add-support-for-QCA956x-SoC.patch
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@@ -24,7 +24,7 @@
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config ATH79_NVRAM
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--- a/arch/mips/ath79/clock.c
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+++ b/arch/mips/ath79/clock.c
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-@@ -524,6 +524,100 @@ static void __init qca955x_clocks_init(v
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+@@ -520,6 +520,100 @@ static void __init qca955x_clocks_init(v
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clk_add_alias("uart", NULL, "ref", NULL);
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}
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@@ -125,7 +125,7 @@
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void __init ath79_clocks_init(void)
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{
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if (soc_is_ar71xx())
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-@@ -540,6 +634,8 @@ void __init ath79_clocks_init(void)
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+@@ -536,6 +630,8 @@ void __init ath79_clocks_init(void)
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qca953x_clocks_init();
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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@@ -219,7 +219,7 @@
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}
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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-@@ -189,6 +189,26 @@ static void qca955x_wmac_setup(void)
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+@@ -184,6 +184,26 @@ static void qca955x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = true;
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}
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@@ -246,7 +246,7 @@
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static bool __init
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ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
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{
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-@@ -392,6 +412,8 @@ void __init ath79_register_wmac(u8 *cal_
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+@@ -387,6 +407,8 @@ void __init ath79_register_wmac(u8 *cal_
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qca953x_wmac_setup();
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else if (soc_is_qca955x())
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qca955x_wmac_setup();
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diff --git a/target/linux/ar71xx/patches-4.4/631-MIPS-ath79-wmac-enable-set-led-pin.patch b/target/linux/ar71xx/patches-4.4/631-MIPS-ath79-wmac-enable-set-led-pin.patch
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index 16a0b909c570b403473346b0c992f9de02b67132..b0e15379787ade16a02363c78c143e878f27a7f2 100644
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--- a/target/linux/ar71xx/patches-4.4/631-MIPS-ath79-wmac-enable-set-led-pin.patch
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+++ b/target/linux/ar71xx/patches-4.4/631-MIPS-ath79-wmac-enable-set-led-pin.patch
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@@ -1,6 +1,6 @@
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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-@@ -400,6 +400,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
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+@@ -395,6 +395,11 @@ void __init ath79_wmac_set_ext_lna_gpio(
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ar934x_set_ext_lna_gpio(chain, gpio);
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}
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diff --git a/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch b/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
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index 8aa5957a7152af27854f6f7c197120b8029cf9e8..b59e43c7712a18e5e81944361c358dfb08c488ea 100644
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--- a/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
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+++ b/target/linux/ar71xx/patches-4.4/640-MIPS-ath79-add-QCA955x-wmac-reset.patch
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@@ -32,7 +32,7 @@
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*/
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--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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-@@ -171,6 +171,27 @@ static void qca953x_wmac_setup(void)
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+@@ -166,6 +166,27 @@ static void qca953x_wmac_setup(void)
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ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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}
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@@ -60,7 +60,7 @@
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static void qca955x_wmac_setup(void)
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{
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u32 t;
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-@@ -187,6 +208,8 @@ static void qca955x_wmac_setup(void)
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+@@ -182,6 +203,8 @@ static void qca955x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = false;
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else
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ath79_wmac_data.is_clk_25mhz = true;
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