Merge 08f493f83d into e8866a04c5
This commit is contained in:
Heiko Wundram
GitHub
commit
1c05d103c2
@ -118,7 +118,7 @@ ar71xx-generic
|
||||
- TL-WR740N (v1, v3, v4, v5)
|
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- TL-WR741N/ND (v1, v2, v4, v5)
|
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- TL-WR743N/ND (v1, v2)
|
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- TL-WR841N/ND (v3, v5, v7, v8, v9)
|
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- TL-WR841N/ND (v3, v5, v7, v8, v9, v10)
|
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- TL-WR842N/ND (v1, v2)
|
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- TL-WR941N/ND (v2, v3, v4, v5)
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- TL-WR2543N/ND (v1)
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||||
|
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@ -0,0 +1,435 @@
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From: Heiko Wundram <modelnine@modelnine.org>
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Date: Mon, Oct 26 2015 14:48:26 +0100
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Subject: backport patches for TP-LINK WR841N/ND v10
|
||||
|
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diff --git a/target/linux/ar71xx/base-files/etc/diag.sh b/target/linux/ar71xx/base-files/etc/diag.sh
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index 6aac86a..9b172a5 100755
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--- a/target/linux/ar71xx/base-files/etc/diag.sh
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+++ b/target/linux/ar71xx/base-files/etc/diag.sh
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@@ -229,7 +229,8 @@ get_status_led() {
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tl-wr720n-v3)
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status_led="tp-link:blue:system"
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;;
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- tl-wr841n-v9)
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+ tl-wr841n-v9 | \
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+ tl-wr841n-v10)
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status_led="tp-link:green:qss"
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;;
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tl-wr2543n)
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diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
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index 315a9fd..fa03d46 100755
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--- a/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
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+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/01_leds
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@@ -367,7 +367,8 @@ tl-wa830re-v2)
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ucidef_set_led_wlan "wlan" "WLAN" "tp-link:green:wlan" "phy0tpt"
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;;
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-tl-wr841n-v9)
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+tl-wr841n-v9 | \
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+tl-wr841n-v10)
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ucidef_set_led_netdev "wan" "WAN" "tp-link:green:wan" "eth1"
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ucidef_set_led_switch "lan1" "LAN1" "tp-link:green:lan1" "switch0" "0x10"
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ucidef_set_led_switch "lan2" "LAN2" "tp-link:green:lan2" "switch0" "0x08"
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diff --git a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
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index 3ccb917..32976b8 100755
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--- a/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
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+++ b/target/linux/ar71xx/base-files/etc/uci-defaults/02_network
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@@ -368,6 +368,7 @@ tl-wr741nd |\
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tl-wr741nd-v4 |\
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tl-wr841n-v7 |\
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tl-wr841n-v9 |\
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+tl-wr841n-v10 |\
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whr-g301n |\
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whr-hp-g300n |\
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whr-hp-gn |\
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diff --git a/target/linux/ar71xx/base-files/lib/ar71xx.sh b/target/linux/ar71xx/base-files/lib/ar71xx.sh
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index 6ba40aa..afd90dd 100755
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--- a/target/linux/ar71xx/base-files/lib/ar71xx.sh
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+++ b/target/linux/ar71xx/base-files/lib/ar71xx.sh
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@@ -703,6 +703,9 @@ ar71xx_board_detect() {
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*"TL-WR841N/ND v9")
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name="tl-wr841n-v9"
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;;
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+ *"TL-WR841N/ND v10")
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+ name="tl-wr841n-v10"
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+ ;;
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*"TL-WR842N/ND v2")
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name="tl-wr842n-v2"
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;;
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diff --git a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
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index 49746c4..4169770 100755
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--- a/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
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+++ b/target/linux/ar71xx/base-files/lib/upgrade/platform.sh
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@@ -324,6 +324,7 @@ platform_check_image() {
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tl-wr841n-v7 | \
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tl-wr841n-v8 | \
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tl-wr841n-v9 | \
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+ tl-wr841n-v10 | \
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tl-wr842n-v2 | \
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tl-wr941nd | \
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tl-wr941nd-v5 | \
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diff --git a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile
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index 53ae3f6..5611617 100644
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--- a/target/linux/ar71xx/image/Makefile
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+++ b/target/linux/ar71xx/image/Makefile
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@@ -1240,6 +1240,7 @@ $(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWA750,tl-wa750re-v1,TL-WA750RE,
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$(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWR841NV8,tl-wr841n-v8,TL-WR841N-v8,ttyS0,115200,0x08410008,1,4Mlzma))
|
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$(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWA830RV2,tl-wa830re-v2,TL-WA830RE-v2,ttyS0,115200,0x08300002,1,4Mlzma))
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$(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWR841NV9,tl-wr841n-v9,TL-WR841N-v9,ttyS0,115200,0x08410009,1,4Mlzma))
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+$(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWR841NV10,tl-wr841n-v10,TL-WR841N-v10,ttyS0,115200,0x08410010,1,4Mlzma))
|
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$(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWR842V2,tl-wr842n-v2,TL-WR842N-v2,ttyS0,115200,0x8420002,1,8Mlzma))
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$(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWA801NV2,tl-wa801nd-v2,TL-WA801ND-v2,ttyS0,115200,0x08010002,1,4Mlzma))
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$(eval $(call SingleProfile,TPLINK-LZMA,64kraw,TLWA850,tl-wa850re-v1,TL-WA850RE,ttyS0,115200,0x08500001,1,4Mlzma))
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@@ -1323,7 +1324,7 @@ $(eval $(call MultiProfile,TLWR720,TLWR720NV3))
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$(eval $(call MultiProfile,TLWR740,TLWR740NV1 TLWR740NV3 TLWR740NV4 TLWR740NV5))
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$(eval $(call MultiProfile,TLWR741,TLWR741NV1 TLWR741NV2 TLWR741NV4 TLWR741NV5))
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$(eval $(call MultiProfile,TLWR743,TLWR743NV1 TLWR743NV2))
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-$(eval $(call MultiProfile,TLWR841,TLWR841NV15 TLWR841NV3 TLWR841NV5 TLWR841NV7 TLWR841NV8 TLWR841NV9))
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+$(eval $(call MultiProfile,TLWR841,TLWR841NV15 TLWR841NV3 TLWR841NV5 TLWR841NV7 TLWR841NV8 TLWR841NV9 TLWR841NV10))
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$(eval $(call MultiProfile,TLWR842,TLWR842V1 TLWR842V2))
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$(eval $(call MultiProfile,TLWR941,TLWR941NV2 TLWR941NV3 TLWR941NV4 TLWR941NV5 TLWR941NV6))
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$(eval $(call MultiProfile,TLWR1043,TLWR1043V1 TLWR1043V2))
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diff --git a/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
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index 00458d2..f45c4c6 100644
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--- a/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
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+++ b/target/linux/ar71xx/patches-3.10/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
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@@ -1,50 +1,7 @@
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-From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
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-Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
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-From: Matthias Schiffer <mschiffer@universe-factory.net>
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-Date: Sat, 29 Mar 2014 20:26:08 +0100
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-Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
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-
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-Note that the clock calculation looks very similar to the QCA955x, but the
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-meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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----
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- arch/mips/ath79/Kconfig | 6 +-
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- arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++
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- arch/mips/ath79/common.c | 4 ++
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- arch/mips/ath79/dev-common.c | 1 +
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- arch/mips/ath79/dev-wmac.c | 20 +++++++
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- arch/mips/ath79/early_printk.c | 1 +
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- arch/mips/ath79/gpio.c | 4 +-
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- arch/mips/ath79/irq.c | 4 ++
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- arch/mips/ath79/setup.c | 8 ++-
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- arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
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- arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
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- 11 files changed, 182 insertions(+), 3 deletions(-)
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-
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---- a/arch/mips/ath79/Kconfig
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-+++ b/arch/mips/ath79/Kconfig
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-@@ -929,6 +929,10 @@ config SOC_AR934X
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- select PCI_AR724X if PCI
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- def_bool n
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-
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-+config SOC_QCA953X
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-+ select USB_ARCH_HAS_EHCI
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-+ def_bool n
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-+
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- config SOC_QCA955X
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- select USB_ARCH_HAS_EHCI
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- select HW_HAS_PCI
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-@@ -972,7 +976,7 @@ config ATH79_DEV_USB
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- def_bool n
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-
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- config ATH79_DEV_WMAC
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-- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
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-+ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
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- def_bool n
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-
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- config ATH79_NVRAM
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---- a/arch/mips/ath79/clock.c
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-+++ b/arch/mips/ath79/clock.c
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-@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
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+diff -urN a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
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+--- a/arch/mips/ath79/clock.c 2015-10-26 12:04:30.109198158 +0100
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++++ b/arch/mips/ath79/clock.c 2015-09-18 16:40:33.076000000 +0200
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+@@ -295,6 +295,82 @@
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iounmap(dpll_base);
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}
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@@ -127,7 +84,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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static void __init qca955x_clocks_init(void)
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{
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u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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-@@ -383,6 +459,8 @@ void __init ath79_clocks_init(void)
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+@@ -383,6 +459,8 @@
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ar933x_clocks_init();
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else if (soc_is_ar934x())
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ar934x_clocks_init();
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@@ -136,9 +93,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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else if (soc_is_qca955x())
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qca955x_clocks_init();
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else
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---- a/arch/mips/ath79/common.c
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-+++ b/arch/mips/ath79/common.c
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-@@ -73,6 +73,8 @@ void ath79_device_reset_set(u32 mask)
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+diff -urN a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
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+--- a/arch/mips/ath79/common.c 2015-10-26 12:04:30.109198158 +0100
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++++ b/arch/mips/ath79/common.c 2015-09-18 16:40:33.076000000 +0200
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+@@ -73,6 +73,8 @@
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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@@ -147,7 +105,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else
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-@@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
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+@@ -101,6 +103,8 @@
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reg = AR933X_RESET_REG_RESET_MODULE;
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else if (soc_is_ar934x())
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reg = AR934X_RESET_REG_RESET_MODULE;
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@@ -156,9 +114,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
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else if (soc_is_qca955x())
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reg = QCA955X_RESET_REG_RESET_MODULE;
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else
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---- a/arch/mips/ath79/dev-common.c
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-+++ b/arch/mips/ath79/dev-common.c
|
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-@@ -100,6 +100,7 @@ void __init ath79_register_uart(void)
|
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+diff -urN a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
|
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+--- a/arch/mips/ath79/dev-common.c 2015-10-26 12:04:30.109198158 +0100
|
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++++ b/arch/mips/ath79/dev-common.c 2015-09-18 16:40:33.076000000 +0200
|
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+@@ -100,6 +100,7 @@
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soc_is_ar724x() ||
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soc_is_ar913x() ||
|
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soc_is_ar934x() ||
|
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@@ -166,9 +125,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
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soc_is_qca955x()) {
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ath79_uart_data[0].uartclk = clk_get_rate(clk);
|
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platform_device_register(&ath79_uart_device);
|
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---- a/arch/mips/ath79/dev-wmac.c
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-+++ b/arch/mips/ath79/dev-wmac.c
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-@@ -101,7 +101,7 @@ static int ar933x_wmac_reset(void)
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+diff -urN a/arch/mips/ath79/dev-wmac.c b/arch/mips/ath79/dev-wmac.c
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+--- a/arch/mips/ath79/dev-wmac.c 2015-10-26 12:04:30.109198158 +0100
|
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++++ b/arch/mips/ath79/dev-wmac.c 2015-09-18 16:40:33.076000000 +0200
|
||||
+@@ -101,7 +101,7 @@
|
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return -ETIMEDOUT;
|
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}
|
||||
|
||||
@@ -177,7 +137,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
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{
|
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return ath79_soc_rev;
|
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}
|
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-@@ -126,7 +126,7 @@ static void __init ar933x_wmac_setup(voi
|
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+@@ -126,7 +126,7 @@
|
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ath79_wmac_data.is_clk_25mhz = true;
|
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|
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if (ath79_soc_rev == 1)
|
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@@ -186,7 +146,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
|
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ath79_wmac_data.external_reset = ar933x_wmac_reset;
|
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}
|
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-@@ -149,6 +149,26 @@ static void ar934x_wmac_setup(void)
|
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+@@ -149,6 +149,26 @@
|
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ath79_wmac_data.is_clk_25mhz = true;
|
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}
|
||||
|
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@@ -213,7 +173,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
static void qca955x_wmac_setup(void)
|
||||
{
|
||||
u32 t;
|
||||
-@@ -366,6 +386,8 @@ void __init ath79_register_wmac(u8 *cal_
|
||||
+@@ -366,6 +386,8 @@
|
||||
ar933x_wmac_setup();
|
||||
else if (soc_is_ar934x())
|
||||
ar934x_wmac_setup();
|
||||
@@ -222,19 +182,22 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
else if (soc_is_qca955x())
|
||||
qca955x_wmac_setup();
|
||||
else
|
||||
---- a/arch/mips/ath79/early_printk.c
|
||||
-+++ b/arch/mips/ath79/early_printk.c
|
||||
-@@ -114,6 +114,7 @@ static void prom_putchar_init(void)
|
||||
+diff -urN a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
|
||||
+--- a/arch/mips/ath79/early_printk.c 2015-10-26 12:04:30.109198158 +0100
|
||||
++++ b/arch/mips/ath79/early_printk.c 2015-10-26 12:13:33.768007483 +0100
|
||||
+@@ -114,6 +114,8 @@
|
||||
case REV_ID_MAJOR_AR9341:
|
||||
case REV_ID_MAJOR_AR9342:
|
||||
case REV_ID_MAJOR_AR9344:
|
||||
+ case REV_ID_MAJOR_QCA9533:
|
||||
++ case REV_ID_MAJOR_QCA9533_V2:
|
||||
case REV_ID_MAJOR_QCA9556:
|
||||
case REV_ID_MAJOR_QCA9558:
|
||||
_prom_putchar = prom_putchar_ar71xx;
|
||||
---- a/arch/mips/ath79/gpio.c
|
||||
-+++ b/arch/mips/ath79/gpio.c
|
||||
-@@ -224,6 +224,8 @@ void __init ath79_gpio_init(void)
|
||||
+diff -urN a/arch/mips/ath79/gpio.c b/arch/mips/ath79/gpio.c
|
||||
+--- a/arch/mips/ath79/gpio.c 2015-10-26 12:04:30.109198158 +0100
|
||||
++++ b/arch/mips/ath79/gpio.c 2015-09-18 16:40:33.076000000 +0200
|
||||
+@@ -224,6 +224,8 @@
|
||||
ath79_gpio_count = AR933X_GPIO_COUNT;
|
||||
else if (soc_is_ar934x())
|
||||
ath79_gpio_count = AR934X_GPIO_COUNT;
|
||||
@@ -243,7 +206,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
else if (soc_is_qca955x())
|
||||
ath79_gpio_count = QCA955X_GPIO_COUNT;
|
||||
else
|
||||
-@@ -231,7 +233,7 @@ void __init ath79_gpio_init(void)
|
||||
+@@ -231,7 +233,7 @@
|
||||
|
||||
ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
|
||||
ath79_gpio_chip.ngpio = ath79_gpio_count;
|
||||
@@ -252,9 +215,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
|
||||
ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
|
||||
}
|
||||
---- a/arch/mips/ath79/irq.c
|
||||
-+++ b/arch/mips/ath79/irq.c
|
||||
-@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
|
||||
+diff -urN a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
|
||||
+--- a/arch/mips/ath79/irq.c 2015-10-26 12:04:30.109198158 +0100
|
||||
++++ b/arch/mips/ath79/irq.c 2015-09-18 16:40:33.076000000 +0200
|
||||
+@@ -106,6 +106,7 @@
|
||||
else if (soc_is_ar724x() ||
|
||||
soc_is_ar933x() ||
|
||||
soc_is_ar934x() ||
|
||||
@@ -262,7 +226,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
soc_is_qca955x())
|
||||
ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
||||
else
|
||||
-@@ -352,6 +353,9 @@ void __init arch_init_irq(void)
|
||||
+@@ -352,6 +353,9 @@
|
||||
} else if (soc_is_ar934x()) {
|
||||
ath79_ip2_handler = ath79_default_ip2_handler;
|
||||
ath79_ip3_handler = ar934x_ip3_handler;
|
||||
@@ -272,12 +236,49 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
} else if (soc_is_qca955x()) {
|
||||
ath79_ip2_handler = ath79_default_ip2_handler;
|
||||
ath79_ip3_handler = ath79_default_ip3_handler;
|
||||
---- a/arch/mips/ath79/setup.c
|
||||
-+++ b/arch/mips/ath79/setup.c
|
||||
-@@ -151,6 +151,12 @@ static void __init ath79_detect_sys_type
|
||||
+diff -urN a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
|
||||
+--- a/arch/mips/ath79/Kconfig 2015-10-26 12:04:30.109198158 +0100
|
||||
++++ b/arch/mips/ath79/Kconfig 2015-09-18 16:40:33.356000000 +0200
|
||||
+@@ -1082,6 +1082,10 @@
|
||||
+ select PCI_AR724X if PCI
|
||||
+ def_bool n
|
||||
+
|
||||
++config SOC_QCA953X
|
||||
++ select USB_ARCH_HAS_EHCI
|
||||
++ def_bool n
|
||||
++
|
||||
+ config SOC_QCA955X
|
||||
+ select USB_ARCH_HAS_EHCI
|
||||
+ select HW_HAS_PCI
|
||||
+@@ -1125,7 +1129,7 @@
|
||||
+ def_bool n
|
||||
+
|
||||
+ config ATH79_DEV_WMAC
|
||||
+- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
|
||||
++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
|
||||
+ def_bool n
|
||||
+
|
||||
+ config ATH79_NVRAM
|
||||
+diff -urN a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
|
||||
+--- a/arch/mips/ath79/setup.c 2015-10-26 12:04:30.109198158 +0100
|
||||
++++ b/arch/mips/ath79/setup.c 2015-10-26 12:25:45.015568505 +0100
|
||||
+@@ -60,6 +60,7 @@
|
||||
+ u32 major;
|
||||
+ u32 minor;
|
||||
+ u32 rev = 0;
|
||||
++ u32 ver = 1;
|
||||
+
|
||||
+ id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
|
||||
+ major = id & REV_ID_MAJOR_MASK;
|
||||
+@@ -152,6 +153,17 @@
|
||||
rev = id & AR934X_REV_ID_REVISION_MASK;
|
||||
break;
|
||||
|
||||
++ case REV_ID_MAJOR_QCA9533_V2:
|
||||
++ ver = 2;
|
||||
++ ath79_soc_rev = 2;
|
||||
++ /* fall through. */
|
||||
++
|
||||
+ case REV_ID_MAJOR_QCA9533:
|
||||
+ ath79_soc = ATH79_SOC_QCA9533;
|
||||
+ chip = "9533";
|
||||
@@ -287,17 +288,26 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
case REV_ID_MAJOR_QCA9556:
|
||||
ath79_soc = ATH79_SOC_QCA9556;
|
||||
chip = "9556";
|
||||
-@@ -169,7 +175,7 @@ static void __init ath79_detect_sys_type
|
||||
+@@ -168,11 +180,12 @@
|
||||
+ panic("ath79: unknown SoC, id:0x%08x", id);
|
||||
+ }
|
||||
|
||||
- ath79_soc_rev = rev;
|
||||
+- ath79_soc_rev = rev;
|
||||
++ if (ver == 1)
|
||||
++ ath79_soc_rev = rev;
|
||||
|
||||
- if (soc_is_qca955x())
|
||||
+- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
||||
+- chip, rev);
|
||||
+ if (soc_is_qca953x() || soc_is_qca955x())
|
||||
- sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
||||
- chip, rev);
|
||||
++ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
|
||||
++ chip, ver, rev);
|
||||
else
|
||||
---- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
-+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
+ sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
|
||||
+ pr_info("SoC: %s\n", ath79_sys_type);
|
||||
+diff -urN a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
||||
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2015-10-26 12:04:30.109198158 +0100
|
||||
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h 2015-10-26 12:09:44.119890545 +0100
|
||||
@@ -106,6 +106,9 @@
|
||||
#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
|
||||
#define AR934X_SRIF_SIZE 0x1000
|
||||
@@ -372,15 +382,16 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
#define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
||||
|
||||
#define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
||||
-@@ -566,6 +612,7 @@
|
||||
+@@ -566,6 +612,8 @@
|
||||
#define REV_ID_MAJOR_AR9341 0x0120
|
||||
#define REV_ID_MAJOR_AR9342 0x1120
|
||||
#define REV_ID_MAJOR_AR9344 0x2120
|
||||
+#define REV_ID_MAJOR_QCA9533 0x0140
|
||||
++#define REV_ID_MAJOR_QCA9533_V2 0x0160
|
||||
#define REV_ID_MAJOR_QCA9556 0x0130
|
||||
#define REV_ID_MAJOR_QCA9558 0x1130
|
||||
|
||||
-@@ -588,6 +635,8 @@
|
||||
+@@ -588,6 +636,8 @@
|
||||
|
||||
#define AR934X_REV_ID_REVISION_MASK 0xf
|
||||
|
||||
@@ -389,7 +400,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
#define QCA955X_REV_ID_REVISION_MASK 0xf
|
||||
|
||||
/*
|
||||
-@@ -641,6 +690,7 @@
|
||||
+@@ -641,6 +691,7 @@
|
||||
#define AR913X_GPIO_COUNT 22
|
||||
#define AR933X_GPIO_COUNT 30
|
||||
#define AR934X_GPIO_COUNT 23
|
||||
@@ -397,9 +408,10 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
#define QCA955X_GPIO_COUNT 24
|
||||
|
||||
/*
|
||||
---- a/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
-+++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
-@@ -32,6 +32,7 @@ enum ath79_soc_type {
|
||||
+diff -urN a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
|
||||
+--- a/arch/mips/include/asm/mach-ath79/ath79.h 2015-10-26 12:04:30.113198090 +0100
|
||||
++++ b/arch/mips/include/asm/mach-ath79/ath79.h 2015-09-18 16:40:33.344000000 +0200
|
||||
+@@ -32,6 +32,7 @@
|
||||
ATH79_SOC_AR9341,
|
||||
ATH79_SOC_AR9342,
|
||||
ATH79_SOC_AR9344,
|
||||
@@ -407,7 +419,7 @@ meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
|
||||
ATH79_SOC_QCA9556,
|
||||
ATH79_SOC_QCA9558,
|
||||
};
|
||||
-@@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
|
||||
+@@ -100,6 +101,16 @@
|
||||
return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
||||
}
|
||||
|
||||
@ -0,0 +1,51 @@
|
||||
From: Heiko Wundram <modelnine@modelnine.org>
|
||||
Date: Mon, Oct 26 2015 14:48:26 +0100
|
||||
Subject: add machine type for WR841N v10
|
||||
|
||||
diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
|
||||
index c28afc6..3b76f74 100644
|
||||
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
|
||||
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-tl-wr841n-v9.c
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
- * TP-LINK TL-WR841N/ND v9
|
||||
+ * TP-LINK TL-WR841N/ND v9/v10
|
||||
*
|
||||
* Copyright (C) 2014 Matthias Schiffer <mschiffer@universe-factory.net>
|
||||
*
|
||||
@@ -136,3 +136,18 @@ static void __init tl_wr841n_v9_setup(void)
|
||||
|
||||
MIPS_MACHINE(ATH79_MACH_TL_WR841N_V9, "TL-WR841N-v9", "TP-LINK TL-WR841N/ND v9",
|
||||
tl_wr841n_v9_setup);
|
||||
+
|
||||
+static void __init tl_wr841n_v10_setup(void)
|
||||
+{
|
||||
+ tl_ap143_setup();
|
||||
+
|
||||
+ ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v9_leds_gpio),
|
||||
+ tl_wr841n_v9_leds_gpio);
|
||||
+
|
||||
+ ath79_register_gpio_keys_polled(1, TL_WR841NV9_KEYS_POLL_INTERVAL,
|
||||
+ ARRAY_SIZE(tl_wr841n_v9_gpio_keys),
|
||||
+ tl_wr841n_v9_gpio_keys);
|
||||
+}
|
||||
+
|
||||
+MIPS_MACHINE(ATH79_MACH_TL_WR841N_V10, "TL-WR841N-v10", "TP-LINK TL-WR841N/ND v10",
|
||||
+ tl_wr841n_v10_setup);
|
||||
diff --git a/target/linux/ar71xx/patches-3.10/730-MIPS-ath79-add-WR841v10-support.patch b/target/linux/ar71xx/patches-3.10/730-MIPS-ath79-add-WR841v10-support.patch
|
||||
new file mode 100644
|
||||
index 0000000..c60b02c
|
||||
--- /dev/null
|
||||
+++ b/target/linux/ar71xx/patches-3.10/730-MIPS-ath79-add-WR841v10-support.patch
|
||||
@@ -0,0 +1,11 @@
|
||||
+diff -urN a/arch/mips/ath79/machtypes.h b/arch/mips/ath79/machtypes.h
|
||||
+--- a/arch/mips/ath79/machtypes.h 2015-10-26 16:09:05.538327997 +0100
|
||||
++++ b/arch/mips/ath79/machtypes.h 2015-10-26 16:23:46.059923783 +0100
|
||||
+@@ -145,6 +145,7 @@
|
||||
+ ATH79_MACH_TL_WR841N_V7, /* TP-LINK TL-WR841N/ND v7 */
|
||||
+ ATH79_MACH_TL_WR841N_V8, /* TP-LINK TL-WR841N/ND v8 */
|
||||
+ ATH79_MACH_TL_WR841N_V9, /* TP-LINK TL-WR841N/ND v9 */
|
||||
++ ATH79_MACH_TL_WR841N_V10, /* TP-LINK TL-WR841N/ND v10 */
|
||||
+ ATH79_MACH_TL_WR842N_V2, /* TP-LINK TL-WR842N/ND v2 */
|
||||
+ ATH79_MACH_TL_WR941ND, /* TP-LINK TL-WR941ND */
|
||||
+ ATH79_MACH_TL_WR941ND_V5, /* TP-LINK TL-WR941ND v5 */
|
||||
963
patches/openwrt/0052-ar71xx-add-support-for-9531-rev2-v1.1.patch
Normal file
963
patches/openwrt/0052-ar71xx-add-support-for-9531-rev2-v1.1.patch
Normal file
@ -0,0 +1,963 @@
|
||||
From: Heiko Wundram <modelnine@modelnine.org>
|
||||
Date: Mon, Oct 26 2015 14:48:26 +0100
|
||||
Subject: add WLAN hardware patch for TP-LINK 841ND v10
|
||||
|
||||
diff -urN a/package/kernel/mac80211/patches/568-ath9k_qca9531_rev2.patch b/package/kernel/mac80211/patches/568-ath9k_qca9531_rev2.patch
|
||||
--- a/package/kernel/mac80211/patches/568-ath9k_qca9531_rev2.patch 1970-01-01 01:00:00.000000000 +0100
|
||||
+++ b/package/kernel/mac80211/patches/568-ath9k_qca9531_rev2.patch 2015-11-30 00:37:58.638264963 +0100
|
||||
@@ -0,0 +1,955 @@
|
||||
+diff -urN a/drivers/net/wireless/ath/ath9k/ar9003_hw.c b/drivers/net/wireless/ath/ath9k/ar9003_hw.c
|
||||
+--- a/drivers/net/wireless/ath/ath9k/ar9003_hw.c 2015-11-29 22:00:47.662902700 +0100
|
||||
++++ b/drivers/net/wireless/ath/ath9k/ar9003_hw.c 2015-11-29 22:11:15.202489300 +0100
|
||||
+@@ -314,10 +314,17 @@
|
||||
+ qca953x_1p0_mac_core);
|
||||
+ INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
|
||||
+ qca953x_1p0_mac_postamble);
|
||||
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
||||
+- qca953x_1p0_baseband_core);
|
||||
+- INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
||||
+- qca953x_1p0_baseband_postamble);
|
||||
++ if (AR_SREV_9531_20(ah)) {
|
||||
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
||||
++ qca953x_2p0_baseband_core);
|
||||
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
||||
++ qca953x_2p0_baseband_postamble);
|
||||
++ } else {
|
||||
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
|
||||
++ qca953x_1p0_baseband_core);
|
||||
++ INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
|
||||
++ qca953x_1p0_baseband_postamble);
|
||||
++ }
|
||||
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
|
||||
+ qca953x_1p0_radio_core);
|
||||
+ INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
|
||||
+@@ -326,12 +333,29 @@
|
||||
+ qca953x_1p0_soc_preamble);
|
||||
+ INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
|
||||
+ qca953x_1p0_soc_postamble);
|
||||
+- INIT_INI_ARRAY(&ah->iniModesRxGain,
|
||||
+- qca953x_1p0_common_wo_xlna_rx_gain_table);
|
||||
+- INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
||||
+- qca953x_1p0_common_wo_xlna_rx_gain_bounds);
|
||||
+- INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
+- qca953x_1p0_modes_no_xpa_tx_gain_table);
|
||||
++
|
||||
++ if (AR_SREV_9531_20(ah)) {
|
||||
++ INIT_INI_ARRAY(&ah->iniModesRxGain,
|
||||
++ qca953x_2p0_common_wo_xlna_rx_gain_table);
|
||||
++ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
||||
++ qca953x_2p0_common_wo_xlna_rx_gain_bounds);
|
||||
++ } else {
|
||||
++ INIT_INI_ARRAY(&ah->iniModesRxGain,
|
||||
++ qca953x_1p0_common_wo_xlna_rx_gain_table);
|
||||
++ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
||||
++ qca953x_1p0_common_wo_xlna_rx_gain_bounds);
|
||||
++ }
|
||||
++
|
||||
++ if (AR_SREV_9531_20(ah))
|
||||
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
++ qca953x_2p0_modes_no_xpa_tx_gain_table);
|
||||
++ else if (AR_SREV_9531_11(ah))
|
||||
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
++ qca953x_1p1_modes_no_xpa_tx_gain_table);
|
||||
++ else
|
||||
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
++ qca953x_1p0_modes_no_xpa_tx_gain_table);
|
||||
++
|
||||
+ INIT_INI_ARRAY(&ah->iniModesFastClock,
|
||||
+ qca953x_1p0_modes_fast_clock);
|
||||
+ } else if (AR_SREV_9580(ah)) {
|
||||
+@@ -511,9 +535,15 @@
|
||||
+ else if (AR_SREV_9550(ah))
|
||||
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
+ ar955x_1p0_modes_xpa_tx_gain_table);
|
||||
+- else if (AR_SREV_9531(ah))
|
||||
++ else if (AR_SREV_9531_10(ah))
|
||||
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
++ qca953x_1p0_modes_xpa_tx_gain_table);
|
||||
++ else if (AR_SREV_9531_11(ah))
|
||||
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
+- qca953x_1p0_modes_xpa_tx_gain_table);
|
||||
++ qca953x_1p1_modes_xpa_tx_gain_table);
|
||||
++ else if (AR_SREV_9531_20(ah))
|
||||
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
++ qca953x_2p0_modes_xpa_tx_gain_table);
|
||||
+ else if (AR_SREV_9580(ah))
|
||||
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
+ ar9580_1p0_lowest_ob_db_tx_gain_table);
|
||||
+@@ -555,7 +585,10 @@
|
||||
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
+ ar955x_1p0_modes_no_xpa_tx_gain_table);
|
||||
+ else if (AR_SREV_9531(ah)) {
|
||||
+- if (AR_SREV_9531_11(ah))
|
||||
++ if (AR_SREV_9531_20(ah))
|
||||
++ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
++ qca953x_2p0_modes_no_xpa_tx_gain_table);
|
||||
++ else if (AR_SREV_9531_11(ah))
|
||||
+ INIT_INI_ARRAY(&ah->iniModesTxGain,
|
||||
+ qca953x_1p1_modes_no_xpa_tx_gain_table);
|
||||
+ else
|
||||
+@@ -782,11 +815,16 @@
|
||||
+ ar955x_1p0_common_wo_xlna_rx_gain_table);
|
||||
+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
||||
+ ar955x_1p0_common_wo_xlna_rx_gain_bounds);
|
||||
+- } else if (AR_SREV_9531(ah)) {
|
||||
++ } else if (AR_SREV_9531_10(ah) || AR_SREV_9531_11(ah)) {
|
||||
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
|
||||
+ qca953x_1p0_common_wo_xlna_rx_gain_table);
|
||||
+ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
||||
+ qca953x_1p0_common_wo_xlna_rx_gain_bounds);
|
||||
++ } else if (AR_SREV_9531_20(ah)) {
|
||||
++ INIT_INI_ARRAY(&ah->iniModesRxGain,
|
||||
++ qca953x_2p0_common_wo_xlna_rx_gain_table);
|
||||
++ INIT_INI_ARRAY(&ah->ini_modes_rx_gain_bounds,
|
||||
++ qca953x_2p0_common_wo_xlna_rx_gain_bounds);
|
||||
+ } else if (AR_SREV_9580(ah))
|
||||
+ INIT_INI_ARRAY(&ah->iniModesRxGain,
|
||||
+ ar9580_1p0_wo_xlna_rx_gain_table);
|
||||
+diff -urN a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
|
||||
+--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c 2015-11-29 22:00:52.922898900 +0100
|
||||
++++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c 2015-11-30 00:34:53.775259900 +0100
|
||||
+@@ -1508,13 +1508,15 @@
|
||||
+ u8 *ini_reloaded)
|
||||
+ {
|
||||
+ unsigned int regWrites = 0;
|
||||
+- u32 modesIndex;
|
||||
++ u32 modesIndex, txgain_index;
|
||||
+
|
||||
+ if (IS_CHAN_5GHZ(chan))
|
||||
+ modesIndex = IS_CHAN_HT40(chan) ? 2 : 1;
|
||||
+ else
|
||||
+ modesIndex = IS_CHAN_HT40(chan) ? 3 : 4;
|
||||
+
|
||||
++ txgain_index = AR_SREV_9531(ah) ? 1 : modesIndex;
|
||||
++
|
||||
+ if (modesIndex == ah->modes_index) {
|
||||
+ *ini_reloaded = false;
|
||||
+ goto set_rfmode;
|
||||
+@@ -1529,7 +1531,7 @@
|
||||
+ ar9003_hw_prog_ini(ah, &ah->ini_radio_post_sys2ant,
|
||||
+ modesIndex);
|
||||
+
|
||||
+- REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
|
||||
++ REG_WRITE_ARRAY(&ah->iniModesTxGain, txgain_index, regWrites);
|
||||
+
|
||||
+ if (AR_SREV_9462_20_OR_LATER(ah)) {
|
||||
+ /*
|
||||
+diff -urN a/drivers/net/wireless/ath/ath9k/ar953x_initvals.h b/drivers/net/wireless/ath/ath9k/ar953x_initvals.h
|
||||
+--- a/drivers/net/wireless/ath/ath9k/ar953x_initvals.h 2015-11-29 22:00:57.439980200 +0100
|
||||
++++ b/drivers/net/wireless/ath/ath9k/ar953x_initvals.h 2015-11-29 21:40:59.221646400 +0100
|
||||
+@@ -20,6 +20,8 @@
|
||||
+
|
||||
+ #define qca953x_1p0_mac_postamble ar9300_2p2_mac_postamble
|
||||
+
|
||||
++#define qca953x_1p0_soc_preamble ar955x_1p0_soc_preamble
|
||||
++
|
||||
+ #define qca953x_1p0_soc_postamble ar9300_2p2_soc_postamble
|
||||
+
|
||||
+ #define qca953x_1p0_common_rx_gain_table ar9300Common_rx_gain_table_2p2
|
||||
+@@ -28,6 +30,10 @@
|
||||
+
|
||||
+ #define qca953x_1p0_modes_fast_clock ar9300Modes_fast_clock_2p2
|
||||
+
|
||||
++#define qca953x_1p0_common_wo_xlna_rx_gain_bounds ar955x_1p0_common_wo_xlna_rx_gain_bounds
|
||||
++
|
||||
++#define qca953x_1p0_common_rx_gain_bounds ar955x_1p0_common_rx_gain_bounds
|
||||
++
|
||||
+ static const u32 qca953x_1p0_mac_core[][2] = {
|
||||
+ /* Addr allmodes */
|
||||
+ {0x00000008, 0x00000000},
|
||||
+@@ -219,7 +225,7 @@
|
||||
+ {0x00009d04, 0x40206c10},
|
||||
+ {0x00009d08, 0x009c4060},
|
||||
+ {0x00009d0c, 0x9883800a},
|
||||
+- {0x00009d10, 0x01884061},
|
||||
++ {0x00009d10, 0x018848c6},
|
||||
+ {0x00009d14, 0x00c0040b},
|
||||
+ {0x00009d18, 0x00000000},
|
||||
+ {0x00009e08, 0x0038230c},
|
||||
+@@ -352,7 +358,7 @@
|
||||
+ {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
|
||||
+ {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
|
||||
+ {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
|
||||
+- {0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcfa10822, 0xcfa10822},
|
||||
++ {0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcfa10820, 0xcfa10820},
|
||||
+ {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
|
||||
+ {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
|
||||
+ {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
|
||||
+@@ -372,7 +378,7 @@
|
||||
+ {0x0000a284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
|
||||
+ {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
|
||||
+ {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
|
||||
+- {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
|
||||
++ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00058d18, 0x00058d18},
|
||||
+ {0x0000a2cc, 0x18c50033, 0x18c43433, 0x18c41033, 0x18c44c33},
|
||||
+ {0x0000a2d0, 0x00041982, 0x00041982, 0x00041982, 0x00041982},
|
||||
+ {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
|
||||
+@@ -490,35 +496,6 @@
|
||||
+ {0x00016540, 0x10804008, 0x10804008, 0x50804000, 0x50804000},
|
||||
+ };
|
||||
+
|
||||
+-static const u32 qca953x_1p0_soc_preamble[][2] = {
|
||||
+- /* Addr allmodes */
|
||||
+- {0x00007000, 0x00000000},
|
||||
+- {0x00007004, 0x00000000},
|
||||
+- {0x00007008, 0x00000000},
|
||||
+- {0x0000700c, 0x00000000},
|
||||
+- {0x0000701c, 0x00000000},
|
||||
+- {0x00007020, 0x00000000},
|
||||
+- {0x00007024, 0x00000000},
|
||||
+- {0x00007028, 0x00000000},
|
||||
+- {0x0000702c, 0x00000000},
|
||||
+- {0x00007030, 0x00000000},
|
||||
+- {0x00007034, 0x00000002},
|
||||
+- {0x00007038, 0x000004c2},
|
||||
+- {0x00007048, 0x00000000},
|
||||
+-};
|
||||
+-
|
||||
+-static const u32 qca953x_1p0_common_rx_gain_bounds[][5] = {
|
||||
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
+- {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
|
||||
+- {0x00009e48, 0x5030201a, 0x5030201a, 0x50302018, 0x50302018},
|
||||
+-};
|
||||
+-
|
||||
+-static const u32 qca953x_1p0_common_wo_xlna_rx_gain_bounds[][5] = {
|
||||
+- /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
+- {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
|
||||
+- {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
|
||||
+-};
|
||||
+-
|
||||
+ static const u32 qca953x_1p0_modes_xpa_tx_gain_table[][2] = {
|
||||
+ /* Addr allmodes */
|
||||
+ {0x0000a2dc, 0xfffd5aaa},
|
||||
+@@ -654,6 +631,666 @@
|
||||
+ /* Addr allmodes */
|
||||
+ {0x0000a2dc, 0xffd5f552},
|
||||
+ {0x0000a2e0, 0xffe60664},
|
||||
++ {0x0000a2e4, 0xfff80780},
|
||||
++ {0x0000a2e8, 0xfffff800},
|
||||
++ {0x0000a410, 0x000050de},
|
||||
++ {0x0000a500, 0x00000061},
|
||||
++ {0x0000a504, 0x04000063},
|
||||
++ {0x0000a508, 0x08000065},
|
||||
++ {0x0000a50c, 0x0c000261},
|
||||
++ {0x0000a510, 0x10000263},
|
||||
++ {0x0000a514, 0x14000265},
|
||||
++ {0x0000a518, 0x18000482},
|
||||
++ {0x0000a51c, 0x1b000484},
|
||||
++ {0x0000a520, 0x1f000486},
|
||||
++ {0x0000a524, 0x240008c2},
|
||||
++ {0x0000a528, 0x28000cc1},
|
||||
++ {0x0000a52c, 0x2d000ce3},
|
||||
++ {0x0000a530, 0x31000ce5},
|
||||
++ {0x0000a534, 0x350010e5},
|
||||
++ {0x0000a538, 0x360012e5},
|
||||
++ {0x0000a53c, 0x380014e5},
|
||||
++ {0x0000a540, 0x3b0018e5},
|
||||
++ {0x0000a544, 0x3d001d04},
|
||||
++ {0x0000a548, 0x3e001d05},
|
||||
++ {0x0000a54c, 0x40001d07},
|
||||
++ {0x0000a550, 0x42001f27},
|
||||
++ {0x0000a554, 0x43001f67},
|
||||
++ {0x0000a558, 0x46001fe7},
|
||||
++ {0x0000a55c, 0x47001f2b},
|
||||
++ {0x0000a560, 0x49001f0d},
|
||||
++ {0x0000a564, 0x4b001ed2},
|
||||
++ {0x0000a568, 0x4c001ed4},
|
||||
++ {0x0000a56c, 0x4e001f15},
|
||||
++ {0x0000a570, 0x4f001ff6},
|
||||
++ {0x0000a574, 0x4f001ff6},
|
||||
++ {0x0000a578, 0x4f001ff6},
|
||||
++ {0x0000a57c, 0x4f001ff6},
|
||||
++ {0x0000a600, 0x00000000},
|
||||
++ {0x0000a604, 0x00000000},
|
||||
++ {0x0000a608, 0x00000000},
|
||||
++ {0x0000a60c, 0x00804201},
|
||||
++ {0x0000a610, 0x01008201},
|
||||
++ {0x0000a614, 0x0180c402},
|
||||
++ {0x0000a618, 0x0180c603},
|
||||
++ {0x0000a61c, 0x0180c603},
|
||||
++ {0x0000a620, 0x01c10603},
|
||||
++ {0x0000a624, 0x01c10704},
|
||||
++ {0x0000a628, 0x02c18b05},
|
||||
++ {0x0000a62c, 0x02c14c07},
|
||||
++ {0x0000a630, 0x01008704},
|
||||
++ {0x0000a634, 0x01c10402},
|
||||
++ {0x0000a638, 0x0301cc07},
|
||||
++ {0x0000a63c, 0x0301cc07},
|
||||
++ {0x0000b2dc, 0xffd5f552},
|
||||
++ {0x0000b2e0, 0xffe60664},
|
||||
++ {0x0000b2e4, 0xfff80780},
|
||||
++ {0x0000b2e8, 0xfffff800},
|
||||
++ {0x00016044, 0x049242db},
|
||||
++ {0x00016048, 0x6c927a70},
|
||||
++ {0x00016444, 0x049242db},
|
||||
++ {0x00016448, 0x6c927a70},
|
||||
++};
|
||||
++
|
||||
++static const u32 qca953x_1p1_modes_xpa_tx_gain_table[][2] = {
|
||||
++ /* Addr allmodes */
|
||||
++ {0x0000a2dc, 0xfffb52aa},
|
||||
++ {0x0000a2e0, 0xfffd64cc},
|
||||
++ {0x0000a2e4, 0xfffe80f0},
|
||||
++ {0x0000a2e8, 0xffffff00},
|
||||
++ {0x0000a410, 0x000050d5},
|
||||
++ {0x0000a500, 0x00000000},
|
||||
++ {0x0000a504, 0x04000002},
|
||||
++ {0x0000a508, 0x08000004},
|
||||
++ {0x0000a50c, 0x0c000006},
|
||||
++ {0x0000a510, 0x1000000a},
|
||||
++ {0x0000a514, 0x1400000c},
|
||||
++ {0x0000a518, 0x1800000e},
|
||||
++ {0x0000a51c, 0x1c000048},
|
||||
++ {0x0000a520, 0x2000004a},
|
||||
++ {0x0000a524, 0x2400004c},
|
||||
++ {0x0000a528, 0x2800004e},
|
||||
++ {0x0000a52c, 0x2b00024a},
|
||||
++ {0x0000a530, 0x2f00024c},
|
||||
++ {0x0000a534, 0x3300024e},
|
||||
++ {0x0000a538, 0x36000668},
|
||||
++ {0x0000a53c, 0x38000669},
|
||||
++ {0x0000a540, 0x3a000868},
|
||||
++ {0x0000a544, 0x3d00086a},
|
||||
++ {0x0000a548, 0x4000086c},
|
||||
++ {0x0000a54c, 0x4200086e},
|
||||
++ {0x0000a550, 0x43000a6e},
|
||||
++ {0x0000a554, 0x43000a6e},
|
||||
++ {0x0000a558, 0x43000a6e},
|
||||
++ {0x0000a55c, 0x43000a6e},
|
||||
++ {0x0000a560, 0x43000a6e},
|
||||
++ {0x0000a564, 0x43000a6e},
|
||||
++ {0x0000a568, 0x43000a6e},
|
||||
++ {0x0000a56c, 0x43000a6e},
|
||||
++ {0x0000a570, 0x43000a6e},
|
||||
++ {0x0000a574, 0x43000a6e},
|
||||
++ {0x0000a578, 0x43000a6e},
|
||||
++ {0x0000a57c, 0x43000a6e},
|
||||
++ {0x0000a600, 0x00000000},
|
||||
++ {0x0000a604, 0x00000000},
|
||||
++ {0x0000a608, 0x00000000},
|
||||
++ {0x0000a60c, 0x03804000},
|
||||
++ {0x0000a610, 0x03804e01},
|
||||
++ {0x0000a614, 0x03804e01},
|
||||
++ {0x0000a618, 0x03804e01},
|
||||
++ {0x0000a61c, 0x04009002},
|
||||
++ {0x0000a620, 0x04009002},
|
||||
++ {0x0000a624, 0x04009002},
|
||||
++ {0x0000a628, 0x04009002},
|
||||
++ {0x0000a62c, 0x04009002},
|
||||
++ {0x0000a630, 0x04009002},
|
||||
++ {0x0000a634, 0x04009002},
|
||||
++ {0x0000a638, 0x04009002},
|
||||
++ {0x0000a63c, 0x04009002},
|
||||
++ {0x0000b2dc, 0xfffb52aa},
|
||||
++ {0x0000b2e0, 0xfffd64cc},
|
||||
++ {0x0000b2e4, 0xfffe80f0},
|
||||
++ {0x0000b2e8, 0xffffff00},
|
||||
++ {0x00016044, 0x024922db},
|
||||
++ {0x00016048, 0x6c927a70},
|
||||
++ {0x00016444, 0x024922db},
|
||||
++ {0x00016448, 0x6c927a70},
|
||||
++};
|
||||
++
|
||||
++static const u32 qca953x_2p0_baseband_core[][2] = {
|
||||
++ /* Addr allmodes */
|
||||
++ {0x00009800, 0xafe68e30},
|
||||
++ {0x00009804, 0xfd14e000},
|
||||
++ {0x00009808, 0x9c0a9f6b},
|
||||
++ {0x0000980c, 0x04900000},
|
||||
++ {0x00009814, 0x0280c00a},
|
||||
++ {0x00009818, 0x00000000},
|
||||
++ {0x0000981c, 0x00020028},
|
||||
++ {0x00009834, 0x6400a190},
|
||||
++ {0x00009838, 0x0108ecff},
|
||||
++ {0x0000983c, 0x14000600},
|
||||
++ {0x00009880, 0x201fff00},
|
||||
++ {0x00009884, 0x00001042},
|
||||
++ {0x000098a4, 0x00200400},
|
||||
++ {0x000098b0, 0x32840bbe},
|
||||
++ {0x000098bc, 0x00000002},
|
||||
++ {0x000098d0, 0x004b6a8e},
|
||||
++ {0x000098d4, 0x00000820},
|
||||
++ {0x000098dc, 0x00000000},
|
||||
++ {0x000098f0, 0x00000000},
|
||||
++ {0x000098f4, 0x00000000},
|
||||
++ {0x00009c04, 0xff55ff55},
|
||||
++ {0x00009c08, 0x0320ff55},
|
||||
++ {0x00009c0c, 0x00000000},
|
||||
++ {0x00009c10, 0x00000000},
|
||||
++ {0x00009c14, 0x00046384},
|
||||
++ {0x00009c18, 0x05b6b440},
|
||||
++ {0x00009c1c, 0x00b6b440},
|
||||
++ {0x00009d00, 0xc080a333},
|
||||
++ {0x00009d04, 0x40206c10},
|
||||
++ {0x00009d08, 0x009c4060},
|
||||
++ {0x00009d0c, 0x9883800a},
|
||||
++ {0x00009d10, 0x018848c6},
|
||||
++ {0x00009d14, 0x00c0040b},
|
||||
++ {0x00009d18, 0x00000000},
|
||||
++ {0x00009e08, 0x0038230c},
|
||||
++ {0x00009e24, 0x990bb515},
|
||||
++ {0x00009e28, 0x0c6f0000},
|
||||
++ {0x00009e30, 0x06336f77},
|
||||
++ {0x00009e34, 0x6af6532f},
|
||||
++ {0x00009e38, 0x0cc80c00},
|
||||
++ {0x00009e40, 0x0d261820},
|
||||
++ {0x00009e4c, 0x00001004},
|
||||
++ {0x00009e50, 0x00ff03f1},
|
||||
++ {0x00009fc0, 0x813e4788},
|
||||
++ {0x00009fc4, 0x0001efb5},
|
||||
++ {0x00009fcc, 0x40000014},
|
||||
++ {0x00009fd0, 0x02993b93},
|
||||
++ {0x0000a20c, 0x00000000},
|
||||
++ {0x0000a220, 0x00000000},
|
||||
++ {0x0000a224, 0x00000000},
|
||||
++ {0x0000a228, 0x10002310},
|
||||
++ {0x0000a23c, 0x00000000},
|
||||
++ {0x0000a244, 0x0c000000},
|
||||
++ {0x0000a248, 0x00000140},
|
||||
++ {0x0000a2a0, 0x00000007},
|
||||
++ {0x0000a2c0, 0x00000007},
|
||||
++ {0x0000a2c8, 0x00000000},
|
||||
++ {0x0000a2d4, 0x00000000},
|
||||
++ {0x0000a2ec, 0x00000000},
|
||||
++ {0x0000a2f0, 0x00000000},
|
||||
++ {0x0000a2f4, 0x00000000},
|
||||
++ {0x0000a2f8, 0x00000000},
|
||||
++ {0x0000a344, 0x00000000},
|
||||
++ {0x0000a34c, 0x00000000},
|
||||
++ {0x0000a350, 0x0000a000},
|
||||
++ {0x0000a364, 0x00000000},
|
||||
++ {0x0000a370, 0x00000000},
|
||||
++ {0x0000a390, 0x00000001},
|
||||
++ {0x0000a394, 0x00000444},
|
||||
++ {0x0000a398, 0x001f0e0f},
|
||||
++ {0x0000a39c, 0x0075393f},
|
||||
++ {0x0000a3a0, 0xb79f6427},
|
||||
++ {0x0000a3a4, 0x000400ff},
|
||||
++ {0x0000a3a8, 0x6a6a6a6a},
|
||||
++ {0x0000a3ac, 0x6a6a6a6a},
|
||||
++ {0x0000a3b0, 0x00c8641a},
|
||||
++ {0x0000a3b4, 0x0000001a},
|
||||
++ {0x0000a3b8, 0x0088642a},
|
||||
++ {0x0000a3bc, 0x000001fa},
|
||||
++ {0x0000a3c0, 0x20202020},
|
||||
++ {0x0000a3c4, 0x22222220},
|
||||
++ {0x0000a3c8, 0x20200020},
|
||||
++ {0x0000a3cc, 0x20202020},
|
||||
++ {0x0000a3d0, 0x20202020},
|
||||
++ {0x0000a3d4, 0x20202020},
|
||||
++ {0x0000a3d8, 0x20202020},
|
||||
++ {0x0000a3dc, 0x20202020},
|
||||
++ {0x0000a3e0, 0x20202020},
|
||||
++ {0x0000a3e4, 0x20202020},
|
||||
++ {0x0000a3e8, 0x20202020},
|
||||
++ {0x0000a3ec, 0x20202020},
|
||||
++ {0x0000a3f0, 0x00000000},
|
||||
++ {0x0000a3f4, 0x00000000},
|
||||
++ {0x0000a3f8, 0x0c9bd380},
|
||||
++ {0x0000a3fc, 0x000f0f01},
|
||||
++ {0x0000a400, 0x8fa91f01},
|
||||
++ {0x0000a404, 0x00000000},
|
||||
++ {0x0000a408, 0x0e79e5c6},
|
||||
++ {0x0000a40c, 0x00820820},
|
||||
++ {0x0000a414, 0x1ce42108},
|
||||
++ {0x0000a418, 0x2d001dce},
|
||||
++ {0x0000a41c, 0x1ce73908},
|
||||
++ {0x0000a420, 0x000001ce},
|
||||
++ {0x0000a424, 0x1ce738e7},
|
||||
++ {0x0000a428, 0x000001ce},
|
||||
++ {0x0000a42c, 0x1ce739ce},
|
||||
++ {0x0000a430, 0x1ce739ce},
|
||||
++ {0x0000a434, 0x00000000},
|
||||
++ {0x0000a438, 0x00001801},
|
||||
++ {0x0000a43c, 0x00100000},
|
||||
++ {0x0000a444, 0x00000000},
|
||||
++ {0x0000a448, 0x05000080},
|
||||
++ {0x0000a44c, 0x00000001},
|
||||
++ {0x0000a450, 0x00010000},
|
||||
++ {0x0000a458, 0x00000000},
|
||||
++ {0x0000a644, 0xbfad9d74},
|
||||
++ {0x0000a648, 0x0048060a},
|
||||
++ {0x0000a64c, 0x00003c37},
|
||||
++ {0x0000a670, 0x03020100},
|
||||
++ {0x0000a674, 0x09080504},
|
||||
++ {0x0000a678, 0x0d0c0b0a},
|
||||
++ {0x0000a67c, 0x13121110},
|
||||
++ {0x0000a680, 0x31301514},
|
||||
++ {0x0000a684, 0x35343332},
|
||||
++ {0x0000a688, 0x00000036},
|
||||
++ {0x0000a690, 0x08000838},
|
||||
++ {0x0000a7cc, 0x00000000},
|
||||
++ {0x0000a7d0, 0x00000000},
|
||||
++ {0x0000a7d4, 0x00000004},
|
||||
++ {0x0000a7dc, 0x00000000},
|
||||
++ {0x0000a8d0, 0x004b6a8e},
|
||||
++ {0x0000a8d4, 0x00000820},
|
||||
++ {0x0000a8dc, 0x00000000},
|
||||
++ {0x0000a8f0, 0x00000000},
|
||||
++ {0x0000a8f4, 0x00000000},
|
||||
++ {0x0000b2d0, 0x00000080},
|
||||
++ {0x0000b2d4, 0x00000000},
|
||||
++ {0x0000b2ec, 0x00000000},
|
||||
++ {0x0000b2f0, 0x00000000},
|
||||
++ {0x0000b2f4, 0x00000000},
|
||||
++ {0x0000b2f8, 0x00000000},
|
||||
++ {0x0000b408, 0x0e79e5c0},
|
||||
++ {0x0000b40c, 0x00820820},
|
||||
++ {0x0000b420, 0x00000000},
|
||||
++};
|
||||
++
|
||||
++static const u32 qca953x_2p0_baseband_postamble[][5] = {
|
||||
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
++ {0x00009810, 0xd00a8005, 0xd00a8005, 0xd00a8011, 0xd00a8011},
|
||||
++ {0x00009820, 0x206a022e, 0x206a022e, 0x206a012e, 0x206a012e},
|
||||
++ {0x00009824, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0, 0x5ac640d0},
|
||||
++ {0x00009828, 0x06903081, 0x06903081, 0x06903881, 0x06903881},
|
||||
++ {0x0000982c, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4, 0x05eea6d4},
|
||||
++ {0x00009830, 0x0000059c, 0x0000059c, 0x0000119c, 0x0000119c},
|
||||
++ {0x00009c00, 0x000000c4, 0x000000c4, 0x000000c4, 0x000000c4},
|
||||
++ {0x00009e00, 0x0372111a, 0x0372111a, 0x037216a0, 0x037216a0},
|
||||
++ {0x00009e04, 0x001c2020, 0x001c2020, 0x001c2020, 0x001c2020},
|
||||
++ {0x00009e0c, 0x6c4000e2, 0x6d4000e2, 0x6d4000e2, 0x6c4000e2},
|
||||
++ {0x00009e10, 0x7ec88d2e, 0x7ec88d2e, 0x7ec84d2e, 0x7ec84d2e},
|
||||
++ {0x00009e14, 0x37b95d5e, 0x37b9605e, 0x3379605e, 0x33795d5e},
|
||||
++ {0x00009e18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
++ {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
|
||||
++ {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
|
||||
++ {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
|
||||
++ {0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcf946222, 0xcf946222},
|
||||
++ {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
|
||||
++ {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
|
||||
++ {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
|
||||
++ {0x0000a204, 0x005c0ec0, 0x005c0ec4, 0x005c0ec4, 0x005c0ec0},
|
||||
++ {0x0000a208, 0x00000104, 0x00000104, 0x00000004, 0x00000004},
|
||||
++ {0x0000a22c, 0x07e26a2f, 0x07e26a2f, 0x01026a2f, 0x01026a2f},
|
||||
++ {0x0000a230, 0x0000000a, 0x00000014, 0x00000016, 0x0000000b},
|
||||
++ {0x0000a234, 0x00000fff, 0x10000fff, 0x10000fff, 0x00000fff},
|
||||
++ {0x0000a238, 0xffb01018, 0xffb01018, 0xffb01018, 0xffb01018},
|
||||
++ {0x0000a250, 0x00000000, 0x00000000, 0x00000210, 0x00000108},
|
||||
++ {0x0000a254, 0x000007d0, 0x00000fa0, 0x00001130, 0x00000898},
|
||||
++ {0x0000a258, 0x02020002, 0x02020002, 0x02020002, 0x02020002},
|
||||
++ {0x0000a25c, 0x01000e0e, 0x01000e0e, 0x01010e0e, 0x01010e0e},
|
||||
++ {0x0000a260, 0x0a021501, 0x0a021501, 0x3a021501, 0x3a021501},
|
||||
++ {0x0000a264, 0x00000e0e, 0x00000e0e, 0x01000e0e, 0x01000e0e},
|
||||
++ {0x0000a280, 0x00000007, 0x00000007, 0x0000000b, 0x0000000b},
|
||||
++ {0x0000a284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
|
||||
++ {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
|
||||
++ {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
|
||||
++ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
|
||||
++ {0x0000a2cc, 0x18c50033, 0x18c43433, 0x18c41033, 0x18c44c33},
|
||||
++ {0x0000a2d0, 0x00041982, 0x00041982, 0x00041982, 0x00041982},
|
||||
++ {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
|
||||
++ {0x0000a358, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
++ {0x0000a830, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
|
||||
++ {0x0000ae04, 0x001c0000, 0x001c0000, 0x001c0000, 0x001c0000},
|
||||
++ {0x0000ae18, 0x00000000, 0x00000000, 0x00000000, 0x00000000},
|
||||
++ {0x0000ae1c, 0x0000019c, 0x0000019c, 0x0000019c, 0x0000019c},
|
||||
++ {0x0000ae20, 0x000001b5, 0x000001b5, 0x000001ce, 0x000001ce},
|
||||
++ {0x0000b284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
|
||||
++};
|
||||
++
|
||||
++static const u32 qca953x_2p0_common_wo_xlna_rx_gain_table[][2] = {
|
||||
++ /* Addr allmodes */
|
||||
++ {0x0000a000, 0x00010000},
|
||||
++ {0x0000a004, 0x00030002},
|
||||
++ {0x0000a008, 0x00050004},
|
||||
++ {0x0000a00c, 0x00810080},
|
||||
++ {0x0000a010, 0x00830082},
|
||||
++ {0x0000a014, 0x01810180},
|
||||
++ {0x0000a018, 0x01830182},
|
||||
++ {0x0000a01c, 0x01850184},
|
||||
++ {0x0000a020, 0x01890188},
|
||||
++ {0x0000a024, 0x018b018a},
|
||||
++ {0x0000a028, 0x018d018c},
|
||||
++ {0x0000a02c, 0x03820190},
|
||||
++ {0x0000a030, 0x03840383},
|
||||
++ {0x0000a034, 0x03880385},
|
||||
++ {0x0000a038, 0x038a0389},
|
||||
++ {0x0000a03c, 0x038c038b},
|
||||
++ {0x0000a040, 0x0390038d},
|
||||
++ {0x0000a044, 0x03920391},
|
||||
++ {0x0000a048, 0x03940393},
|
||||
++ {0x0000a04c, 0x03960395},
|
||||
++ {0x0000a050, 0x00000000},
|
||||
++ {0x0000a054, 0x00000000},
|
||||
++ {0x0000a058, 0x00000000},
|
||||
++ {0x0000a05c, 0x00000000},
|
||||
++ {0x0000a060, 0x00000000},
|
||||
++ {0x0000a064, 0x00000000},
|
||||
++ {0x0000a068, 0x00000000},
|
||||
++ {0x0000a06c, 0x00000000},
|
||||
++ {0x0000a070, 0x00000000},
|
||||
++ {0x0000a074, 0x00000000},
|
||||
++ {0x0000a078, 0x00000000},
|
||||
++ {0x0000a07c, 0x00000000},
|
||||
++ {0x0000a080, 0x29292929},
|
||||
++ {0x0000a084, 0x29292929},
|
||||
++ {0x0000a088, 0x29292929},
|
||||
++ {0x0000a08c, 0x29292929},
|
||||
++ {0x0000a090, 0x22292929},
|
||||
++ {0x0000a094, 0x1d1d2222},
|
||||
++ {0x0000a098, 0x0c111117},
|
||||
++ {0x0000a09c, 0x00030303},
|
||||
++ {0x0000a0a0, 0x00000000},
|
||||
++ {0x0000a0a4, 0x00000000},
|
||||
++ {0x0000a0a8, 0x00000000},
|
||||
++ {0x0000a0ac, 0x00000000},
|
||||
++ {0x0000a0b0, 0x00000000},
|
||||
++ {0x0000a0b4, 0x00000000},
|
||||
++ {0x0000a0b8, 0x00000000},
|
||||
++ {0x0000a0bc, 0x00000000},
|
||||
++ {0x0000a0c0, 0x001f0000},
|
||||
++ {0x0000a0c4, 0x01000101},
|
||||
++ {0x0000a0c8, 0x011e011f},
|
||||
++ {0x0000a0cc, 0x011c011d},
|
||||
++ {0x0000a0d0, 0x02030204},
|
||||
++ {0x0000a0d4, 0x02010202},
|
||||
++ {0x0000a0d8, 0x021f0200},
|
||||
++ {0x0000a0dc, 0x0302021e},
|
||||
++ {0x0000a0e0, 0x03000301},
|
||||
++ {0x0000a0e4, 0x031e031f},
|
||||
++ {0x0000a0e8, 0x0402031d},
|
||||
++ {0x0000a0ec, 0x04000401},
|
||||
++ {0x0000a0f0, 0x041e041f},
|
||||
++ {0x0000a0f4, 0x0502041d},
|
||||
++ {0x0000a0f8, 0x05000501},
|
||||
++ {0x0000a0fc, 0x051e051f},
|
||||
++ {0x0000a100, 0x06010602},
|
||||
++ {0x0000a104, 0x061f0600},
|
||||
++ {0x0000a108, 0x061d061e},
|
||||
++ {0x0000a10c, 0x07020703},
|
||||
++ {0x0000a110, 0x07000701},
|
||||
++ {0x0000a114, 0x00000000},
|
||||
++ {0x0000a118, 0x00000000},
|
||||
++ {0x0000a11c, 0x00000000},
|
||||
++ {0x0000a120, 0x00000000},
|
||||
++ {0x0000a124, 0x00000000},
|
||||
++ {0x0000a128, 0x00000000},
|
||||
++ {0x0000a12c, 0x00000000},
|
||||
++ {0x0000a130, 0x00000000},
|
||||
++ {0x0000a134, 0x00000000},
|
||||
++ {0x0000a138, 0x00000000},
|
||||
++ {0x0000a13c, 0x00000000},
|
||||
++ {0x0000a140, 0x001f0000},
|
||||
++ {0x0000a144, 0x01000101},
|
||||
++ {0x0000a148, 0x011e011f},
|
||||
++ {0x0000a14c, 0x011c011d},
|
||||
++ {0x0000a150, 0x02030204},
|
||||
++ {0x0000a154, 0x02010202},
|
||||
++ {0x0000a158, 0x021f0200},
|
||||
++ {0x0000a15c, 0x0302021e},
|
||||
++ {0x0000a160, 0x03000301},
|
||||
++ {0x0000a164, 0x031e031f},
|
||||
++ {0x0000a168, 0x0402031d},
|
||||
++ {0x0000a16c, 0x04000401},
|
||||
++ {0x0000a170, 0x041e041f},
|
||||
++ {0x0000a174, 0x0502041d},
|
||||
++ {0x0000a178, 0x05000501},
|
||||
++ {0x0000a17c, 0x051e051f},
|
||||
++ {0x0000a180, 0x06010602},
|
||||
++ {0x0000a184, 0x061f0600},
|
||||
++ {0x0000a188, 0x061d061e},
|
||||
++ {0x0000a18c, 0x07020703},
|
||||
++ {0x0000a190, 0x07000701},
|
||||
++ {0x0000a194, 0x00000000},
|
||||
++ {0x0000a198, 0x00000000},
|
||||
++ {0x0000a19c, 0x00000000},
|
||||
++ {0x0000a1a0, 0x00000000},
|
||||
++ {0x0000a1a4, 0x00000000},
|
||||
++ {0x0000a1a8, 0x00000000},
|
||||
++ {0x0000a1ac, 0x00000000},
|
||||
++ {0x0000a1b0, 0x00000000},
|
||||
++ {0x0000a1b4, 0x00000000},
|
||||
++ {0x0000a1b8, 0x00000000},
|
||||
++ {0x0000a1bc, 0x00000000},
|
||||
++ {0x0000a1c0, 0x00000000},
|
||||
++ {0x0000a1c4, 0x00000000},
|
||||
++ {0x0000a1c8, 0x00000000},
|
||||
++ {0x0000a1cc, 0x00000000},
|
||||
++ {0x0000a1d0, 0x00000000},
|
||||
++ {0x0000a1d4, 0x00000000},
|
||||
++ {0x0000a1d8, 0x00000000},
|
||||
++ {0x0000a1dc, 0x00000000},
|
||||
++ {0x0000a1e0, 0x00000000},
|
||||
++ {0x0000a1e4, 0x00000000},
|
||||
++ {0x0000a1e8, 0x00000000},
|
||||
++ {0x0000a1ec, 0x00000000},
|
||||
++ {0x0000a1f0, 0x00000396},
|
||||
++ {0x0000a1f4, 0x00000396},
|
||||
++ {0x0000a1f8, 0x00000396},
|
||||
++ {0x0000a1fc, 0x00000196},
|
||||
++ {0x0000b000, 0x00010000},
|
||||
++ {0x0000b004, 0x00030002},
|
||||
++ {0x0000b008, 0x00050004},
|
||||
++ {0x0000b00c, 0x00810080},
|
||||
++ {0x0000b010, 0x00830082},
|
||||
++ {0x0000b014, 0x01810180},
|
||||
++ {0x0000b018, 0x01830182},
|
||||
++ {0x0000b01c, 0x01850184},
|
||||
++ {0x0000b020, 0x02810280},
|
||||
++ {0x0000b024, 0x02830282},
|
||||
++ {0x0000b028, 0x02850284},
|
||||
++ {0x0000b02c, 0x02890288},
|
||||
++ {0x0000b030, 0x028b028a},
|
||||
++ {0x0000b034, 0x0388028c},
|
||||
++ {0x0000b038, 0x038a0389},
|
||||
++ {0x0000b03c, 0x038c038b},
|
||||
++ {0x0000b040, 0x0390038d},
|
||||
++ {0x0000b044, 0x03920391},
|
||||
++ {0x0000b048, 0x03940393},
|
||||
++ {0x0000b04c, 0x03960395},
|
||||
++ {0x0000b050, 0x00000000},
|
||||
++ {0x0000b054, 0x00000000},
|
||||
++ {0x0000b058, 0x00000000},
|
||||
++ {0x0000b05c, 0x00000000},
|
||||
++ {0x0000b060, 0x00000000},
|
||||
++ {0x0000b064, 0x00000000},
|
||||
++ {0x0000b068, 0x00000000},
|
||||
++ {0x0000b06c, 0x00000000},
|
||||
++ {0x0000b070, 0x00000000},
|
||||
++ {0x0000b074, 0x00000000},
|
||||
++ {0x0000b078, 0x00000000},
|
||||
++ {0x0000b07c, 0x00000000},
|
||||
++ {0x0000b080, 0x32323232},
|
||||
++ {0x0000b084, 0x2f2f3232},
|
||||
++ {0x0000b088, 0x23282a2d},
|
||||
++ {0x0000b08c, 0x1c1e2123},
|
||||
++ {0x0000b090, 0x14171919},
|
||||
++ {0x0000b094, 0x0e0e1214},
|
||||
++ {0x0000b098, 0x03050707},
|
||||
++ {0x0000b09c, 0x00030303},
|
||||
++ {0x0000b0a0, 0x00000000},
|
||||
++ {0x0000b0a4, 0x00000000},
|
||||
++ {0x0000b0a8, 0x00000000},
|
||||
++ {0x0000b0ac, 0x00000000},
|
||||
++ {0x0000b0b0, 0x00000000},
|
||||
++ {0x0000b0b4, 0x00000000},
|
||||
++ {0x0000b0b8, 0x00000000},
|
||||
++ {0x0000b0bc, 0x00000000},
|
||||
++ {0x0000b0c0, 0x003f0020},
|
||||
++ {0x0000b0c4, 0x00400041},
|
||||
++ {0x0000b0c8, 0x0140005f},
|
||||
++ {0x0000b0cc, 0x0160015f},
|
||||
++ {0x0000b0d0, 0x017e017f},
|
||||
++ {0x0000b0d4, 0x02410242},
|
||||
++ {0x0000b0d8, 0x025f0240},
|
||||
++ {0x0000b0dc, 0x027f0260},
|
||||
++ {0x0000b0e0, 0x0341027e},
|
||||
++ {0x0000b0e4, 0x035f0340},
|
||||
++ {0x0000b0e8, 0x037f0360},
|
||||
++ {0x0000b0ec, 0x04400441},
|
||||
++ {0x0000b0f0, 0x0460045f},
|
||||
++ {0x0000b0f4, 0x0541047f},
|
||||
++ {0x0000b0f8, 0x055f0540},
|
||||
++ {0x0000b0fc, 0x057f0560},
|
||||
++ {0x0000b100, 0x06400641},
|
||||
++ {0x0000b104, 0x0660065f},
|
||||
++ {0x0000b108, 0x067e067f},
|
||||
++ {0x0000b10c, 0x07410742},
|
||||
++ {0x0000b110, 0x075f0740},
|
||||
++ {0x0000b114, 0x077f0760},
|
||||
++ {0x0000b118, 0x07800781},
|
||||
++ {0x0000b11c, 0x07a0079f},
|
||||
++ {0x0000b120, 0x07c107bf},
|
||||
++ {0x0000b124, 0x000007c0},
|
||||
++ {0x0000b128, 0x00000000},
|
||||
++ {0x0000b12c, 0x00000000},
|
||||
++ {0x0000b130, 0x00000000},
|
||||
++ {0x0000b134, 0x00000000},
|
||||
++ {0x0000b138, 0x00000000},
|
||||
++ {0x0000b13c, 0x00000000},
|
||||
++ {0x0000b140, 0x003f0020},
|
||||
++ {0x0000b144, 0x00400041},
|
||||
++ {0x0000b148, 0x0140005f},
|
||||
++ {0x0000b14c, 0x0160015f},
|
||||
++ {0x0000b150, 0x017e017f},
|
||||
++ {0x0000b154, 0x02410242},
|
||||
++ {0x0000b158, 0x025f0240},
|
||||
++ {0x0000b15c, 0x027f0260},
|
||||
++ {0x0000b160, 0x0341027e},
|
||||
++ {0x0000b164, 0x035f0340},
|
||||
++ {0x0000b168, 0x037f0360},
|
||||
++ {0x0000b16c, 0x04400441},
|
||||
++ {0x0000b170, 0x0460045f},
|
||||
++ {0x0000b174, 0x0541047f},
|
||||
++ {0x0000b178, 0x055f0540},
|
||||
++ {0x0000b17c, 0x057f0560},
|
||||
++ {0x0000b180, 0x06400641},
|
||||
++ {0x0000b184, 0x0660065f},
|
||||
++ {0x0000b188, 0x067e067f},
|
||||
++ {0x0000b18c, 0x07410742},
|
||||
++ {0x0000b190, 0x075f0740},
|
||||
++ {0x0000b194, 0x077f0760},
|
||||
++ {0x0000b198, 0x07800781},
|
||||
++ {0x0000b19c, 0x07a0079f},
|
||||
++ {0x0000b1a0, 0x07c107bf},
|
||||
++ {0x0000b1a4, 0x000007c0},
|
||||
++ {0x0000b1a8, 0x00000000},
|
||||
++ {0x0000b1ac, 0x00000000},
|
||||
++ {0x0000b1b0, 0x00000000},
|
||||
++ {0x0000b1b4, 0x00000000},
|
||||
++ {0x0000b1b8, 0x00000000},
|
||||
++ {0x0000b1bc, 0x00000000},
|
||||
++ {0x0000b1c0, 0x00000000},
|
||||
++ {0x0000b1c4, 0x00000000},
|
||||
++ {0x0000b1c8, 0x00000000},
|
||||
++ {0x0000b1cc, 0x00000000},
|
||||
++ {0x0000b1d0, 0x00000000},
|
||||
++ {0x0000b1d4, 0x00000000},
|
||||
++ {0x0000b1d8, 0x00000000},
|
||||
++ {0x0000b1dc, 0x00000000},
|
||||
++ {0x0000b1e0, 0x00000000},
|
||||
++ {0x0000b1e4, 0x00000000},
|
||||
++ {0x0000b1e8, 0x00000000},
|
||||
++ {0x0000b1ec, 0x00000000},
|
||||
++ {0x0000b1f0, 0x00000396},
|
||||
++ {0x0000b1f4, 0x00000396},
|
||||
++ {0x0000b1f8, 0x00000396},
|
||||
++ {0x0000b1fc, 0x00000196},
|
||||
++};
|
||||
++
|
||||
++static const u32 qca953x_2p0_common_wo_xlna_rx_gain_bounds[][5] = {
|
||||
++ /* Addr 5G_HT20 5G_HT40 2G_HT40 2G_HT20 */
|
||||
++ {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
|
||||
++ {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
|
||||
++};
|
||||
++
|
||||
++static const u32 qca953x_2p0_modes_xpa_tx_gain_table[][2] = {
|
||||
++ /* Addr allmodes */
|
||||
++ {0x0000a2dc, 0xfffb52aa},
|
||||
++ {0x0000a2e0, 0xfffd64cc},
|
||||
++ {0x0000a2e4, 0xfffe80f0},
|
||||
++ {0x0000a2e8, 0xffffff00},
|
||||
++ {0x0000a410, 0x000050d5},
|
||||
++ {0x0000a500, 0x00000000},
|
||||
++ {0x0000a504, 0x04000002},
|
||||
++ {0x0000a508, 0x08000004},
|
||||
++ {0x0000a50c, 0x0c000006},
|
||||
++ {0x0000a510, 0x1000000a},
|
||||
++ {0x0000a514, 0x1400000c},
|
||||
++ {0x0000a518, 0x1800000e},
|
||||
++ {0x0000a51c, 0x1c000048},
|
||||
++ {0x0000a520, 0x2000004a},
|
||||
++ {0x0000a524, 0x2400004c},
|
||||
++ {0x0000a528, 0x2800004e},
|
||||
++ {0x0000a52c, 0x2b00024a},
|
||||
++ {0x0000a530, 0x2f00024c},
|
||||
++ {0x0000a534, 0x3300024e},
|
||||
++ {0x0000a538, 0x36000668},
|
||||
++ {0x0000a53c, 0x38000669},
|
||||
++ {0x0000a540, 0x3a000868},
|
||||
++ {0x0000a544, 0x3d00086a},
|
||||
++ {0x0000a548, 0x4000086c},
|
||||
++ {0x0000a54c, 0x4200086e},
|
||||
++ {0x0000a550, 0x43000a6e},
|
||||
++ {0x0000a554, 0x43000a6e},
|
||||
++ {0x0000a558, 0x43000a6e},
|
||||
++ {0x0000a55c, 0x43000a6e},
|
||||
++ {0x0000a560, 0x43000a6e},
|
||||
++ {0x0000a564, 0x43000a6e},
|
||||
++ {0x0000a568, 0x43000a6e},
|
||||
++ {0x0000a56c, 0x43000a6e},
|
||||
++ {0x0000a570, 0x43000a6e},
|
||||
++ {0x0000a574, 0x43000a6e},
|
||||
++ {0x0000a578, 0x43000a6e},
|
||||
++ {0x0000a57c, 0x43000a6e},
|
||||
++ {0x0000a600, 0x00000000},
|
||||
++ {0x0000a604, 0x00000000},
|
||||
++ {0x0000a608, 0x00000000},
|
||||
++ {0x0000a60c, 0x03804000},
|
||||
++ {0x0000a610, 0x03804e01},
|
||||
++ {0x0000a614, 0x03804e01},
|
||||
++ {0x0000a618, 0x03804e01},
|
||||
++ {0x0000a61c, 0x04009002},
|
||||
++ {0x0000a620, 0x04009002},
|
||||
++ {0x0000a624, 0x04009002},
|
||||
++ {0x0000a628, 0x04009002},
|
||||
++ {0x0000a62c, 0x04009002},
|
||||
++ {0x0000a630, 0x04009002},
|
||||
++ {0x0000a634, 0x04009002},
|
||||
++ {0x0000a638, 0x04009002},
|
||||
++ {0x0000a63c, 0x04009002},
|
||||
++ {0x0000b2dc, 0xfffb52aa},
|
||||
++ {0x0000b2e0, 0xfffd64cc},
|
||||
++ {0x0000b2e4, 0xfffe80f0},
|
||||
++ {0x0000b2e8, 0xffffff00},
|
||||
++ {0x00016044, 0x024922db},
|
||||
++ {0x00016048, 0x6c927a70},
|
||||
++ {0x00016444, 0x024922db},
|
||||
++ {0x00016448, 0x6c927a70},
|
||||
++};
|
||||
++
|
||||
++static const u32 qca953x_2p0_modes_no_xpa_tx_gain_table[][2] = {
|
||||
++ /* Addr allmodes */
|
||||
++ {0x0000a2dc, 0xffd5f552},
|
||||
++ {0x0000a2e0, 0xffe60664},
|
||||
+ {0x0000a2e4, 0xfff80780},
|
||||
+ {0x0000a2e8, 0xfffff800},
|
||||
+ {0x0000a410, 0x000050de},
|
||||
+diff -urN a/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h
|
||||
+--- a/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h 2015-11-29 22:00:41.537115500 +0100
|
||||
++++ b/drivers/net/wireless/ath/ath9k/ar955x_1p0_initvals.h 2015-11-29 21:39:33.371522000 +0100
|
||||
+@@ -63,7 +63,7 @@
|
||||
+ {0x00009e1c, 0x0001cf9c, 0x0001cf9c, 0x00021f9c, 0x00021f9c},
|
||||
+ {0x00009e20, 0x000003b5, 0x000003b5, 0x000003ce, 0x000003ce},
|
||||
+ {0x00009e2c, 0x0000001c, 0x0000001c, 0x00000021, 0x00000021},
|
||||
+- {0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcfa10822, 0xcfa10822},
|
||||
++ {0x00009e3c, 0xcfa10820, 0xcfa10820, 0xcfa10820, 0xcfa10820},
|
||||
+ {0x00009e44, 0xfe321e27, 0xfe321e27, 0xfe291e27, 0xfe291e27},
|
||||
+ {0x00009e48, 0x5030201a, 0x5030201a, 0x50302012, 0x50302012},
|
||||
+ {0x00009fc8, 0x0003f000, 0x0003f000, 0x0001a000, 0x0001a000},
|
||||
+@@ -83,7 +83,7 @@
|
||||
+ {0x0000a284, 0x00000000, 0x00000000, 0x00000010, 0x00000010},
|
||||
+ {0x0000a288, 0x00000110, 0x00000110, 0x00000110, 0x00000110},
|
||||
+ {0x0000a28c, 0x00022222, 0x00022222, 0x00022222, 0x00022222},
|
||||
+- {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00158d18, 0x00158d18},
|
||||
++ {0x0000a2c4, 0x00158d18, 0x00158d18, 0x00058d18, 0x00058d18},
|
||||
+ {0x0000a2cc, 0x18c50033, 0x18c43433, 0x18c41033, 0x18c44c33},
|
||||
+ {0x0000a2d0, 0x00041982, 0x00041982, 0x00041982, 0x00041982},
|
||||
+ {0x0000a2d8, 0x7999a83b, 0x7999a83b, 0x7999a83b, 0x7999a83b},
|
||||
+@@ -507,7 +507,7 @@
|
||||
+ {0x00009d04, 0x40206c10},
|
||||
+ {0x00009d08, 0x009c4060},
|
||||
+ {0x00009d0c, 0x9883800a},
|
||||
+- {0x00009d10, 0x01834061},
|
||||
++ {0x00009d10, 0x01884061},
|
||||
+ {0x00009d14, 0x00c0040b},
|
||||
+ {0x00009d18, 0x00000000},
|
||||
+ {0x00009e08, 0x0038230c},
|
||||
+@@ -545,9 +545,9 @@
|
||||
+ {0x0000a370, 0x00000000},
|
||||
+ {0x0000a390, 0x00000001},
|
||||
+ {0x0000a394, 0x00000444},
|
||||
+- {0x0000a398, 0x1f020503},
|
||||
+- {0x0000a39c, 0x29180c03},
|
||||
+- {0x0000a3a0, 0x9a8b6844},
|
||||
++ {0x0000a398, 0x001f0e0f},
|
||||
++ {0x0000a39c, 0x0075393f},
|
||||
++ {0x0000a3a0, 0xb79f6427},
|
||||
+ {0x0000a3a4, 0x00000000},
|
||||
+ {0x0000a3a8, 0xaaaaaaaa},
|
||||
+ {0x0000a3ac, 0x3c466478},
|
||||
+diff -urN a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
|
||||
+--- a/drivers/net/wireless/ath/ath9k/reg.h 2015-11-29 22:00:58.754125800 +0100
|
||||
++++ b/drivers/net/wireless/ath/ath9k/reg.h 2015-11-30 00:33:28.950312700 +0100
|
||||
+@@ -813,6 +813,7 @@
|
||||
+ #define AR_SREV_VERSION_9531 0x500
|
||||
+ #define AR_SREV_REVISION_9531_10 0
|
||||
+ #define AR_SREV_REVISION_9531_11 1
|
||||
++#define AR_SREV_REVISION_9531_20 2
|
||||
+
|
||||
+ #define AR_SREV_5416(_ah) \
|
||||
+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \
|
||||
+@@ -965,6 +966,9 @@
|
||||
+ #define AR_SREV_9531_11(_ah) \
|
||||
+ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \
|
||||
+ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_11))
|
||||
++#define AR_SREV_9531_20(_ah) \
|
||||
++ (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9531) && \
|
||||
++ ((_ah)->hw_version.macRev == AR_SREV_REVISION_9531_20))
|
||||
+
|
||||
+ /* NOTE: When adding chips newer than Peacock, add chip check here */
|
||||
+ #define AR_SREV_9580_10_OR_LATER(_ah) \
|
||||
@ -50,13 +50,14 @@ $(eval $(call GluonProfile,TLWA801))
|
||||
$(eval $(call GluonModel,TLWA801,tl-wa801nd-v1,tp-link-tl-wa801n-nd-v1))
|
||||
$(eval $(call GluonModel,TLWA801,tl-wa801nd-v2,tp-link-tl-wa801n-nd-v2))
|
||||
|
||||
# TL-WR841N/ND v3, v5, v7, v8, v9
|
||||
# TL-WR841N/ND v3, v5, v7, v8, v9, v10
|
||||
$(eval $(call GluonProfile,TLWR841))
|
||||
$(eval $(call GluonModel,TLWR841,tl-wr841nd-v3,tp-link-tl-wr841n-nd-v3))
|
||||
$(eval $(call GluonModel,TLWR841,tl-wr841nd-v5,tp-link-tl-wr841n-nd-v5))
|
||||
$(eval $(call GluonModel,TLWR841,tl-wr841nd-v7,tp-link-tl-wr841n-nd-v7))
|
||||
$(eval $(call GluonModel,TLWR841,tl-wr841n-v8,tp-link-tl-wr841n-nd-v8))
|
||||
$(eval $(call GluonModel,TLWR841,tl-wr841n-v9,tp-link-tl-wr841n-nd-v9))
|
||||
$(eval $(call GluonModel,TLWR841,tl-wr841n-v10,tp-link-tl-wr841n-nd-v10))
|
||||
|
||||
# TL-WR842N/ND v1, v2
|
||||
$(eval $(call GluonProfile,TLWR842))
|
||||
|
||||
Loading…
Reference in New Issue
Block a user