Update OpenWrt base

This also reverts commit 24d8695d8ceeb09d6c84bcd6ee4ffe087c9b386b...

modules

@@ -1,7 +1,7 @@
 GLUON_FEEDS='openwrt gluon routing luci'
 
 OPENWRT_REPO=git://git.openwrt.org/15.05/openwrt.git
-OPENWRT_COMMIT=23395d539f4a45d8bed611e7f9c64275cd1cce0e
+OPENWRT_COMMIT=eadf19c0b43d2f75f196ea8d875a08c7c348530c
 
 PACKAGES_OPENWRT_REPO=git://github.com/openwrt/packages.git
 PACKAGES_OPENWRT_COMMIT=9622fe984bba3a4547f48bc507ebaba7637eb2b0

patches/openwrt/0015-ar71xx-make-bootconsole-wait-for-both-THRE-and-TEMT.patch

@@ -1,85 +0,0 @@
-From: Matthias Schiffer <mschiffer@universe-factory.net>
-Date: Thu, 24 Mar 2016 18:30:26 +0100
-Subject: ar71xx: make bootconsole wait for both THRE and TEMT
-
-Original commit message:
-
-    MIPS: ath79: make bootconsole wait for both THRE and TEMT
-
-    This makes the ath79 bootconsole behave the same way as the generic 8250
-    bootconsole.
-
-    Also waiting for TEMT (transmit buffer is empty) instead of just THRE
-    (transmit buffer is not full) ensures that all characters have been
-    transmitted before the real serial driver starts reconfiguring the serial
-    controller (which would sometimes result in garbage being transmitted.)
-    This change does not cause a visible performance loss.
-
-    In addition, this seems to fix a hang observed in certain configurations on
-    many AR7xxx/AR9xxx SoCs during autoconfig of the real serial driver.
-
-    A more complete follow-up patch will disable 8250 autoconfig for ath79
-    altogether (the serial controller is detected as a 16550A, which is not
-    fully compatible with the ath79 serial, and the autoconfig may lead to
-    undefined behavior on ath79.)
-
-diff --git a/target/linux/ar71xx/patches-3.18/103-MIPS-ath79-make-bootconsole-wait-for-both-THRE-and-T.patch b/target/linux/ar71xx/patches-3.18/103-MIPS-ath79-make-bootconsole-wait-for-both-THRE-and-T.patch
-new file mode 100644
-index 0000000..7be14ab
---- /dev/null
-+++ b/target/linux/ar71xx/patches-3.18/103-MIPS-ath79-make-bootconsole-wait-for-both-THRE-and-T.patch
-@@ -0,0 +1,54 @@
-+From f1ba020af5076172c9d29006a747ccf40027fedc Mon Sep 17 00:00:00 2001
-+Message-Id: <f1ba020af5076172c9d29006a747ccf40027fedc.1458840219.git.mschiffer@universe-factory.net>
-+From: Matthias Schiffer <mschiffer@universe-factory.net>
-+Date: Thu, 24 Mar 2016 15:34:05 +0100
-+Subject: [PATCH] MIPS: ath79: make bootconsole wait for both THRE and TEMT
-+
-+This makes the ath79 bootconsole behave the same way as the generic 8250
-+bootconsole.
-+
-+Also waiting for TEMT (transmit buffer is empty) instead of just THRE
-+(transmit buffer is not full) ensures that all characters have been
-+transmitted before the real serial driver starts reconfiguring the serial
-+controller (which would sometimes result in garbage being transmitted.)
-+This change does not cause a visible performance loss.
-+
-+In addition, this seems to fix a hang observed in certain configurations on
-+many AR7xxx/AR9xxx SoCs during autoconfig of the real serial driver.
-+
-+A more complete follow-up patch will disable 8250 autoconfig for ath79
-+altogether (the serial controller is detected as a 16550A, which is not
-+fully compatible with the ath79 serial, and the autoconfig may lead to
-+undefined behavior on ath79.)
-+
-+Cc: <stable@vger.kernel.org>
-+Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
-+---
-+ arch/mips/ath79/early_printk.c | 6 ++++--
-+ 1 file changed, 4 insertions(+), 2 deletions(-)
-+
-+diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
-+index b955faf..d1adc59 100644
-+--- a/arch/mips/ath79/early_printk.c
-++++ b/arch/mips/ath79/early_printk.c
-+@@ -31,13 +31,15 @@ static inline void prom_putchar_wait(void __iomem *reg, u32 mask, u32 val)
-+ 	} while (1);
-+ }
-+ 
-++#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
-++
-+ static void prom_putchar_ar71xx(unsigned char ch)
-+ {
-+ 	void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
-+ 
-+-	prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
-++	prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
-+ 	__raw_writel(ch, base + UART_TX * 4);
-+-	prom_putchar_wait(base + UART_LSR * 4, UART_LSR_THRE, UART_LSR_THRE);
-++	prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
-+ }
-+ 
-+ static void prom_putchar_ar933x(unsigned char ch)
-+-- 
-+2.7.4
-+

patches/openwrt/0023-ar71xx-Add-TL-WR841N-ND-v11-support.patch

@@ -1,43 +0,0 @@
-From: Matthias Schiffer <mschiffer@universe-factory.net>
-Date: Mon, 25 Apr 2016 18:07:13 +0200
-Subject: ar71xx: Add TL-WR841N/ND v11 support
-
-This patch adds support for the TP-Link TL-WR841N/ND to trunk. It is
-similar to the already supported v10 - see [1]. I have added support
-based on that topic; in the meantime it has been confirmed working
-(see the forum thread, and also [2]).
-
-Signed-off by Stijn Segers <francesco.borromini@inventati.org>
-
-[1]: https://forum.openwrt.org/viewtopic.php?id=61309
-[2]: https://forum.openwrt.org/viewtopic.php?id=63657
-
-Backport of r49099
-
-diff --git a/target/linux/ar71xx/image/Makefile b/target/linux/ar71xx/image/Makefile
-index 1a399ab..d2538c8 100644
---- a/target/linux/ar71xx/image/Makefile
-+++ b/target/linux/ar71xx/image/Makefile
-@@ -569,6 +569,13 @@ define Device/tl-wr841-v10
-     TPLINK_HWID := 0x08410010
- endef
- 
-+define Device/tl-wr841-v11
-+   $(Device/tplink-4mlzma)
-+   BOARDNAME := TL-WR841N-v9
-+   DEVICE_PROFILE := TLWR841
-+   TPLINK_HWID := 0x08410011
-+endef
-+
- define Device/tl-wr842n-v2
-     $(Device/tplink-8mlzma)
-     BOARDNAME := TL-WR842N-v2
-@@ -589,7 +596,7 @@ define Device/tl-wr847n-v8
-     DEVICE_PROFILE := TLWR841
-     TPLINK_HWID := 0x08470008
- endef
--TARGET_DEVICES += tl-wr841-v8 tl-wr841-v9 tl-wr841-v10 tl-wr842n-v2 tl-wr843nd-v1 tl-wr847n-v8
-+TARGET_DEVICES += tl-wr841-v8 tl-wr841-v9 tl-wr841-v10 tl-wr841-v11 tl-wr842n-v2 tl-wr843nd-v1 tl-wr847n-v8
- 
- define Device/tl-wr941nd-v5
-     $(Device/tplink-4mlzma)

targets/ar71xx-generic/profiles.mk

@@ -16,7 +16,7 @@ $(eval $(call GluonModelAlias,CPE510,tp-link-cpe510-v1.0,tp-link-cpe520-v1.1))
 
 # TL-WA701N/ND v1, v2
 $(eval $(call GluonProfile,TLWA701))
-$(eval $(call GluonModel,TLWA701,tl-wa701nd-v1,tp-link-tl-wa701n-nd-v1))
+$(eval $(call GluonModel,TLWA701,tl-wa701n-v1,tp-link-tl-wa701n-nd-v1))
 $(eval $(call GluonModel,TLWA701,tl-wa701nd-v2,tp-link-tl-wa701n-nd-v2))
 
 # TL-WA7510 v1
@@ -58,13 +58,13 @@ $(eval $(call GluonModel,TLWA801,tl-wa801nd-v2,tp-link-tl-wa801n-nd-v2))
 
 # TL-WR841N/ND v3, v5, v7, v8, v9, v10, v11
 $(eval $(call GluonProfile,TLWR841))
-$(eval $(call GluonModel,TLWR841,tl-wr841-v3,tp-link-tl-wr841n-nd-v3))
-$(eval $(call GluonModel,TLWR841,tl-wr841-v5,tp-link-tl-wr841n-nd-v5))
-$(eval $(call GluonModel,TLWR841,tl-wr841-v7,tp-link-tl-wr841n-nd-v7))
-$(eval $(call GluonModel,TLWR841,tl-wr841-v8,tp-link-tl-wr841n-nd-v8))
-$(eval $(call GluonModel,TLWR841,tl-wr841-v9,tp-link-tl-wr841n-nd-v9))
-$(eval $(call GluonModel,TLWR841,tl-wr841-v10,tp-link-tl-wr841n-nd-v10))
-$(eval $(call GluonModel,TLWR841,tl-wr841-v11,tp-link-tl-wr841n-nd-v11))
+$(eval $(call GluonModel,TLWR841,tl-wr841nd-v3,tp-link-tl-wr841n-nd-v3))
+$(eval $(call GluonModel,TLWR841,tl-wr841nd-v5,tp-link-tl-wr841n-nd-v5))
+$(eval $(call GluonModel,TLWR841,tl-wr841nd-v7,tp-link-tl-wr841n-nd-v7))
+$(eval $(call GluonModel,TLWR841,tl-wr841n-v8,tp-link-tl-wr841n-nd-v8))
+$(eval $(call GluonModel,TLWR841,tl-wr841n-v9,tp-link-tl-wr841n-nd-v9))
+$(eval $(call GluonModel,TLWR841,tl-wr841n-v10,tp-link-tl-wr841n-nd-v10))
+$(eval $(call GluonModel,TLWR841,tl-wr841n-v11,tp-link-tl-wr841n-nd-v11))
 
 # TL-WR842N/ND v1, v2
 $(eval $(call GluonProfile,TLWR842))