141 lines
4.7 KiB
Diff
141 lines
4.7 KiB
Diff
From: Matthias Schiffer <mschiffer@universe-factory.net>
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Date: Fri, 18 Apr 2014 18:30:05 +0200
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Subject: mac80211: ath9k: add support for QCA953x
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This adds the following patches by Sujith Manoharan from ath9k-devel:
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ath9k: Add QCA953x WMAC platform support
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ath9k: Disable AR_INTR_SYNC_HOST1_FATAL for QCA953x
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ath9k: Fix temperature compensation
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diff --git a/package/mac80211/patches/567-ath9k-qca953x-support.patch b/package/mac80211/patches/567-ath9k-qca953x-support.patch
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new file mode 100644
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index 0000000..e73083a
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--- /dev/null
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+++ b/package/mac80211/patches/567-ath9k-qca953x-support.patch
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@@ -0,0 +1,124 @@
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+--- a/drivers/net/wireless/ath/ath9k/ahb.c
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++++ b/drivers/net/wireless/ath/ath9k/ahb.c
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+@@ -39,6 +39,10 @@ static const struct platform_device_id a
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+ .name = "qca955x_wmac",
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+ .driver_data = AR9300_DEVID_QCA955X,
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+ },
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++ {
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++ .name = "qca953x_wmac",
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++ .driver_data = AR9300_DEVID_AR953X,
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++ },
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+ {},
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+ };
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+
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+--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
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++++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.c
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+@@ -4792,43 +4792,54 @@ static void ar9003_hw_power_control_over
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+
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+ tempslope:
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+ if (AR_SREV_9550(ah) || AR_SREV_9531(ah)) {
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++ u8 txmask = (eep->baseEepHeader.txrxMask & 0xf0) >> 4;
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++
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+ /*
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+ * AR955x has tempSlope register for each chain.
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+ * Check whether temp_compensation feature is enabled or not.
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+ */
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+ if (eep->baseEepHeader.featureEnable & 0x1) {
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+ if (frequency < 4000) {
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+- REG_RMW_FIELD(ah, AR_PHY_TPC_19,
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+- AR_PHY_TPC_19_ALPHA_THERM,
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+- eep->base_ext2.tempSlopeLow);
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+- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
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+- AR_PHY_TPC_19_ALPHA_THERM,
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+- temp_slope);
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+- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
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+- AR_PHY_TPC_19_ALPHA_THERM,
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+- eep->base_ext2.tempSlopeHigh);
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++ if (txmask & BIT(0))
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++ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
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++ AR_PHY_TPC_19_ALPHA_THERM,
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++ eep->base_ext2.tempSlopeLow);
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++ if (txmask & BIT(1))
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++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
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++ AR_PHY_TPC_19_ALPHA_THERM,
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++ temp_slope);
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++ if (txmask & BIT(2))
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++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
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++ AR_PHY_TPC_19_ALPHA_THERM,
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++ eep->base_ext2.tempSlopeHigh);
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+ } else {
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+- REG_RMW_FIELD(ah, AR_PHY_TPC_19,
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+- AR_PHY_TPC_19_ALPHA_THERM,
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+- temp_slope);
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+- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
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+- AR_PHY_TPC_19_ALPHA_THERM,
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+- temp_slope1);
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+- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
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+- AR_PHY_TPC_19_ALPHA_THERM,
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+- temp_slope2);
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++ if (txmask & BIT(0))
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++ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
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++ AR_PHY_TPC_19_ALPHA_THERM,
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++ temp_slope);
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++ if (txmask & BIT(1))
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++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
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++ AR_PHY_TPC_19_ALPHA_THERM,
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++ temp_slope1);
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++ if (txmask & BIT(2))
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++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
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++ AR_PHY_TPC_19_ALPHA_THERM,
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++ temp_slope2);
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+ }
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+ } else {
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+ /*
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+ * If temp compensation is not enabled,
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+ * set all registers to 0.
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+ */
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+- REG_RMW_FIELD(ah, AR_PHY_TPC_19,
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+- AR_PHY_TPC_19_ALPHA_THERM, 0);
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+- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
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+- AR_PHY_TPC_19_ALPHA_THERM, 0);
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+- REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
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+- AR_PHY_TPC_19_ALPHA_THERM, 0);
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++ if (txmask & BIT(0))
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++ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
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++ AR_PHY_TPC_19_ALPHA_THERM, 0);
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++ if (txmask & BIT(1))
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++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
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++ AR_PHY_TPC_19_ALPHA_THERM, 0);
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++ if (txmask & BIT(2))
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++ REG_RMW_FIELD(ah, AR_PHY_TPC_19_B2,
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++ AR_PHY_TPC_19_ALPHA_THERM, 0);
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+ }
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+ } else {
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+ REG_RMW_FIELD(ah, AR_PHY_TPC_19,
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+--- a/drivers/net/wireless/ath/ath9k/hw.c
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++++ b/drivers/net/wireless/ath/ath9k/hw.c
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+@@ -901,7 +901,7 @@ static void ath9k_hw_init_interrupt_mask
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+ AR_IMR_RXORN |
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+ AR_IMR_BCNMISC;
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+
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+- if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
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++ if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
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+ sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
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+
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+ if (AR_SREV_9300_20_OR_LATER(ah)) {
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+@@ -3104,6 +3104,7 @@ static struct {
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+ { AR_SREV_VERSION_9462, "9462" },
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+ { AR_SREV_VERSION_9550, "9550" },
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+ { AR_SREV_VERSION_9565, "9565" },
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++ { AR_SREV_VERSION_9531, "9531" },
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+ };
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+
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+ /* For devices with external radios */
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+--- a/drivers/net/wireless/ath/ath9k/mac.c
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++++ b/drivers/net/wireless/ath/ath9k/mac.c
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+@@ -837,7 +837,7 @@ void ath9k_hw_enable_interrupts(struct a
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+ return;
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+ }
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+
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+- if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
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++ if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah))
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+ sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
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+
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+ async_mask = AR_INTR_MAC_IRQ;
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