547 lines
18 KiB
Diff
547 lines
18 KiB
Diff
From: Matthias Schiffer <mschiffer@universe-factory.net>
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Date: Sat, 29 Mar 2014 21:55:41 +0100
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Subject: ar71xx: add support for QCA953x SoC
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diff --git a/target/linux/ar71xx/config-3.3 b/target/linux/ar71xx/config-3.3
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index dfc5bf2..1c3ba3c 100644
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--- a/target/linux/ar71xx/config-3.3
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+++ b/target/linux/ar71xx/config-3.3
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@@ -40,11 +40,11 @@ CONFIG_ATH79_MACH_EW_DORIN=y
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CONFIG_ATH79_MACH_HORNET_UB=y
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CONFIG_ATH79_MACH_JA76PF=y
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CONFIG_ATH79_MACH_JWAP003=y
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+CONFIG_ATH79_MACH_MR600=y
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CONFIG_ATH79_MACH_MZK_W04NU=y
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CONFIG_ATH79_MACH_MZK_W300NH=y
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CONFIG_ATH79_MACH_NBG460N=y
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CONFIG_ATH79_MACH_OM2P=y
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-CONFIG_ATH79_MACH_MR600=y
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CONFIG_ATH79_MACH_PB42=y
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CONFIG_ATH79_MACH_PB44=y
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CONFIG_ATH79_MACH_PB92=y
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@@ -214,6 +214,7 @@ CONFIG_SOC_AR724X=y
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CONFIG_SOC_AR913X=y
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CONFIG_SOC_AR933X=y
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CONFIG_SOC_AR934X=y
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+CONFIG_SOC_QCA953X=y
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CONFIG_SOC_QCA955X=y
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CONFIG_SPI=y
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CONFIG_SPI_AP83=y
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diff --git a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
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index 5a0b950..1a9b0df 100644
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--- a/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
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+++ b/target/linux/ar71xx/files/arch/mips/ath79/dev-eth.c
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@@ -195,6 +195,7 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
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case ATH79_SOC_AR7241:
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case ATH79_SOC_AR9330:
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case ATH79_SOC_AR9331:
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+ case ATH79_SOC_QCA9533:
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mdio_dev = &ath79_mdio1_device;
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mdio_data = &ath79_mdio1_data;
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break;
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@@ -250,6 +251,11 @@ void __init ath79_register_mdio(unsigned int id, u32 phy_mask)
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}
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mdio_data->is_ar934x = 1;
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break;
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+
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+ case ATH79_SOC_QCA9533:
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+ mdio_data->builtin_switch = 1;
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+ break;
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+
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case ATH79_SOC_QCA9558:
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if (id == 1)
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mdio_data->builtin_switch = 1;
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@@ -540,6 +546,7 @@ static void __init ath79_init_eth_pll_data(unsigned int id)
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case ATH79_SOC_AR9341:
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case ATH79_SOC_AR9342:
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case ATH79_SOC_AR9344:
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+ case ATH79_SOC_QCA9533:
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case ATH79_SOC_QCA9558:
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pll_10 = AR934X_PLL_VAL_10;
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pll_100 = AR934X_PLL_VAL_100;
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@@ -596,6 +603,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
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case ATH79_SOC_AR7241:
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case ATH79_SOC_AR9330:
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case ATH79_SOC_AR9331:
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+ case ATH79_SOC_QCA9533:
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pdata->phy_if_mode = PHY_INTERFACE_MODE_MII;
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break;
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@@ -645,6 +653,7 @@ static int __init ath79_setup_phy_if_mode(unsigned int id,
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case ATH79_SOC_AR7241:
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case ATH79_SOC_AR9330:
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case ATH79_SOC_AR9331:
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+ case ATH79_SOC_QCA9533:
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pdata->phy_if_mode = PHY_INTERFACE_MODE_GMII;
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break;
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@@ -882,6 +891,37 @@ void __init ath79_register_eth(unsigned int id)
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pdata->fifo_cfg3 = 0x01f00140;
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break;
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+ case ATH79_SOC_QCA9533:
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+ if (id == 0) {
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+ pdata->reset_bit = AR933X_RESET_GE0_MAC |
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+ AR933X_RESET_GE0_MDIO;
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+ pdata->set_speed = ath79_set_speed_dummy;
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+
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+ pdata->phy_mask = BIT(4);
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+ } else {
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+ pdata->reset_bit = AR933X_RESET_GE1_MAC |
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+ AR933X_RESET_GE1_MDIO;
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+ pdata->set_speed = ath79_set_speed_dummy;
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+
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+ pdata->speed = SPEED_1000;
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+ pdata->duplex = DUPLEX_FULL;
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+ pdata->switch_data = &ath79_switch_data;
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+
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+ ath79_switch_data.phy_poll_mask |= BIT(4);
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+ }
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+
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+ pdata->ddr_flush = ath79_ddr_no_flush;
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+ pdata->has_gbit = 1;
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+ pdata->is_ar724x = 1;
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+
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+ if (!pdata->fifo_cfg1)
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+ pdata->fifo_cfg1 = 0x0010ffff;
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+ if (!pdata->fifo_cfg2)
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+ pdata->fifo_cfg2 = 0x015500aa;
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+ if (!pdata->fifo_cfg3)
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+ pdata->fifo_cfg3 = 0x01f00140;
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+ break;
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+
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case ATH79_SOC_AR9341:
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case ATH79_SOC_AR9342:
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case ATH79_SOC_AR9344:
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@@ -953,6 +993,7 @@ void __init ath79_register_eth(unsigned int id)
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case ATH79_SOC_AR7241:
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case ATH79_SOC_AR9330:
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case ATH79_SOC_AR9331:
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+ case ATH79_SOC_QCA9533:
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pdata->mii_bus_dev = &ath79_mdio1_device.dev;
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break;
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diff --git a/target/linux/ar71xx/patches-3.3/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch b/target/linux/ar71xx/patches-3.3/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
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new file mode 100644
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index 0000000..4c9e761
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--- /dev/null
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+++ b/target/linux/ar71xx/patches-3.3/707-MIPS-ath79-add-support-for-QCA953x-SoC.patch
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@@ -0,0 +1,417 @@
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+From 5300a7cd7ed2f88488ddba62947b9c6bb9663777 Mon Sep 17 00:00:00 2001
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+Message-Id: <5300a7cd7ed2f88488ddba62947b9c6bb9663777.1396122227.git.mschiffer@universe-factory.net>
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+From: Matthias Schiffer <mschiffer@universe-factory.net>
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+Date: Sat, 29 Mar 2014 20:26:08 +0100
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+Subject: [PATCH 1/2] MIPS: ath79: add support for QCA953x SoC
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+
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+Note that the clock calculation looks very similar to the QCA955x, but actually
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+some bits' meanings are slightly different.
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+---
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+ arch/mips/ath79/Kconfig | 6 +-
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+ arch/mips/ath79/clock.c | 78 ++++++++++++++++++++++++++
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+ arch/mips/ath79/common.c | 4 ++
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+ arch/mips/ath79/dev-common.c | 1 +
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+ arch/mips/ath79/dev-wmac.c | 20 +++++++
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+ arch/mips/ath79/early_printk.c | 1 +
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+ arch/mips/ath79/gpio.c | 4 +-
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+ arch/mips/ath79/irq.c | 4 ++
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+ arch/mips/ath79/setup.c | 8 ++-
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+ arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 48 ++++++++++++++++
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+ arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
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+ 11 files changed, 182 insertions(+), 3 deletions(-)
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+
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+--- a/arch/mips/ath79/Kconfig
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++++ b/arch/mips/ath79/Kconfig
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+@@ -688,6 +688,10 @@ config SOC_AR934X
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+ select PCI_AR724X if PCI
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+ def_bool n
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+
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++config SOC_QCA953X
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++ select USB_ARCH_HAS_EHCI
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++ def_bool n
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++
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+ config SOC_QCA955X
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+ select USB_ARCH_HAS_EHCI
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+ select HW_HAS_PCI
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+@@ -731,7 +735,7 @@ config ATH79_DEV_USB
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+ def_bool n
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+
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+ config ATH79_DEV_WMAC
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+- depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
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++ depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
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+ def_bool n
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+
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+ config ATH79_NVRAM
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+--- a/arch/mips/ath79/clock.c
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++++ b/arch/mips/ath79/clock.c
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+@@ -295,6 +295,82 @@ static void __init ar934x_clocks_init(vo
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+ iounmap(dpll_base);
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+ }
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+
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++static void __init qca953x_clocks_init(void)
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++{
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++ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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++ u32 cpu_pll, ddr_pll;
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++ u32 bootstrap;
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++
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++ bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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++ if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
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++ ath79_ref_clk.rate = 40 * 1000 * 1000;
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++ else
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++ ath79_ref_clk.rate = 25 * 1000 * 1000;
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++
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++ pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
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++ out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
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++ QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
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++ ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
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++ QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
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++ nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
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++ QCA953X_PLL_CPU_CONFIG_NINT_MASK;
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++ frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
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++ QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
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++
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++ cpu_pll = nint * ath79_ref_clk.rate / ref_div;
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++ cpu_pll += frac * (ath79_ref_clk.rate >> 6) / ref_div;
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++ cpu_pll /= (1 << out_div);
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++
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++ pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
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++ out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
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++ QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
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++ ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
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++ QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
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++ nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
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++ QCA953X_PLL_DDR_CONFIG_NINT_MASK;
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++ frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
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++ QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
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++
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++ ddr_pll = nint * ath79_ref_clk.rate / ref_div;
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++ ddr_pll += frac * (ath79_ref_clk.rate >> 6) / (ref_div << 4);
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++ ddr_pll /= (1 << out_div);
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++
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++ clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
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++
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++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
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++ QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
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++
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++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
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++ ath79_cpu_clk.rate = ath79_ref_clk.rate;
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++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
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++ ath79_cpu_clk.rate = cpu_pll / (postdiv + 1);
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++ else
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++ ath79_cpu_clk.rate = ddr_pll / (postdiv + 1);
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++
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++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
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++ QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
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++
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++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
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++ ath79_ddr_clk.rate = ath79_ref_clk.rate;
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++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
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++ ath79_ddr_clk.rate = ddr_pll / (postdiv + 1);
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++ else
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++ ath79_ddr_clk.rate = cpu_pll / (postdiv + 1);
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++
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++ postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
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++ QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
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++
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++ if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
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++ ath79_ahb_clk.rate = ath79_ref_clk.rate;
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++ else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
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++ ath79_ahb_clk.rate = ddr_pll / (postdiv + 1);
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++ else
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++ ath79_ahb_clk.rate = cpu_pll / (postdiv + 1);
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++
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++ ath79_wdt_clk.rate = ath79_ref_clk.rate;
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++ ath79_uart_clk.rate = ath79_ref_clk.rate;
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++}
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++
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+ static void __init qca955x_clocks_init(void)
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+ {
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+ u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
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+@@ -383,6 +459,8 @@ void __init ath79_clocks_init(void)
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+ ar933x_clocks_init();
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+ else if (soc_is_ar934x())
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+ ar934x_clocks_init();
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++ else if (soc_is_qca953x())
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++ qca953x_clocks_init();
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+ else if (soc_is_qca955x())
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+ qca955x_clocks_init();
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+ else
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+--- a/arch/mips/ath79/common.c
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++++ b/arch/mips/ath79/common.c
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+@@ -74,6 +74,8 @@ void ath79_device_reset_set(u32 mask)
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+ else if (soc_is_ar934x() ||
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+ soc_is_qca955x())
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+ reg = AR934X_RESET_REG_RESET_MODULE;
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++ else if (soc_is_qca953x())
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++ reg = QCA953X_RESET_REG_RESET_MODULE;
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+ else
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+ BUG();
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+
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+@@ -101,6 +103,8 @@ void ath79_device_reset_clear(u32 mask)
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+ else if (soc_is_ar934x() ||
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+ soc_is_qca955x())
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+ reg = AR934X_RESET_REG_RESET_MODULE;
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++ else if (soc_is_qca953x())
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++ reg = QCA953X_RESET_REG_RESET_MODULE;
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+ else
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+ BUG();
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+
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+--- a/arch/mips/ath79/dev-common.c
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++++ b/arch/mips/ath79/dev-common.c
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+@@ -100,6 +100,7 @@ void __init ath79_register_uart(void)
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+ soc_is_ar724x() ||
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+ soc_is_ar913x() ||
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+ soc_is_ar934x() ||
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++ soc_is_qca953x() ||
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+ soc_is_qca955x()) {
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+ ath79_uart_data[0].uartclk = clk_get_rate(clk);
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+ platform_device_register(&ath79_uart_device);
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+--- a/arch/mips/ath79/dev-wmac.c
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++++ b/arch/mips/ath79/dev-wmac.c
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+@@ -99,7 +99,7 @@ static int ar933x_wmac_reset(void)
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+ return -ETIMEDOUT;
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+ }
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+
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+-static int ar933x_r1_get_wmac_revision(void)
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++static int ar93xx_get_soc_revision(void)
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+ {
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+ return ath79_soc_rev;
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+ }
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+@@ -124,7 +124,7 @@ static void __init ar933x_wmac_setup(voi
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+ ath79_wmac_data.is_clk_25mhz = true;
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+
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+ if (ath79_soc_rev == 1)
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+- ath79_wmac_data.get_mac_revision = ar933x_r1_get_wmac_revision;
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++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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+
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+ ath79_wmac_data.external_reset = ar933x_wmac_reset;
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+ }
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+@@ -147,6 +147,26 @@ static void ar934x_wmac_setup(void)
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+ ath79_wmac_data.is_clk_25mhz = true;
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+ }
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+
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++static void qca953x_wmac_setup(void)
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++{
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++ u32 t;
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++
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++ ath79_wmac_device.name = "qca953x_wmac";
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++
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++ ath79_wmac_resources[0].start = QCA953X_WMAC_BASE;
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++ ath79_wmac_resources[0].end = QCA953X_WMAC_BASE + QCA953X_WMAC_SIZE - 1;
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++ ath79_wmac_resources[1].start = ATH79_CPU_IRQ_IP2;
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++ ath79_wmac_resources[1].end = ATH79_CPU_IRQ_IP2;
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++
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++ t = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
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++ if (t & QCA953X_BOOTSTRAP_REF_CLK_40)
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++ ath79_wmac_data.is_clk_25mhz = false;
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++ else
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++ ath79_wmac_data.is_clk_25mhz = true;
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++
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++ ath79_wmac_data.get_mac_revision = ar93xx_get_soc_revision;
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++}
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++
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+ static void qca955x_wmac_setup(void)
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+ {
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+ u32 t;
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+@@ -314,6 +334,8 @@ void __init ath79_register_wmac(u8 *cal_
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+ ar933x_wmac_setup();
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+ else if (soc_is_ar934x())
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+ ar934x_wmac_setup();
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++ else if (soc_is_qca953x())
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++ qca953x_wmac_setup();
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+ else if (soc_is_qca955x())
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+ qca955x_wmac_setup();
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+ else
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+--- a/arch/mips/ath79/early_printk.c
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++++ b/arch/mips/ath79/early_printk.c
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+@@ -114,6 +114,7 @@ static void prom_putchar_init(void)
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+ case REV_ID_MAJOR_AR9341:
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+ case REV_ID_MAJOR_AR9342:
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+ case REV_ID_MAJOR_AR9344:
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++ case REV_ID_MAJOR_QCA9533:
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+ case REV_ID_MAJOR_QCA9558:
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+ _prom_putchar = prom_putchar_ar71xx;
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+ break;
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+--- a/arch/mips/ath79/gpio.c
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++++ b/arch/mips/ath79/gpio.c
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+@@ -240,6 +240,8 @@ void __init ath79_gpio_init(void)
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+ ath79_gpio_count = AR933X_GPIO_COUNT;
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+ else if (soc_is_ar934x())
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+ ath79_gpio_count = AR934X_GPIO_COUNT;
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++ else if (soc_is_qca953x())
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++ ath79_gpio_count = QCA953X_GPIO_COUNT;
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+ else if (soc_is_qca955x())
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+ ath79_gpio_count = QCA955X_GPIO_COUNT;
|
|
+ else
|
|
+@@ -247,7 +249,7 @@ void __init ath79_gpio_init(void)
|
|
+
|
|
+ ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE);
|
|
+ ath79_gpio_chip.ngpio = ath79_gpio_count;
|
|
+- if (soc_is_ar934x() || soc_is_qca955x()) {
|
|
++ if (soc_is_ar934x() || soc_is_qca953x() || soc_is_qca955x()) {
|
|
+ ath79_gpio_chip.direction_input = ar934x_gpio_direction_input;
|
|
+ ath79_gpio_chip.direction_output = ar934x_gpio_direction_output;
|
|
+ }
|
|
+--- a/arch/mips/ath79/irq.c
|
|
++++ b/arch/mips/ath79/irq.c
|
|
+@@ -106,6 +106,7 @@ static void __init ath79_misc_irq_init(v
|
|
+ else if (soc_is_ar724x() ||
|
|
+ soc_is_ar933x() ||
|
|
+ soc_is_ar934x() ||
|
|
++ soc_is_qca953x() ||
|
|
+ soc_is_qca955x())
|
|
+ ath79_misc_irq_chip.irq_ack = ar724x_misc_irq_ack;
|
|
+ else
|
|
+@@ -352,6 +353,9 @@ void __init arch_init_irq(void)
|
|
+ } else if (soc_is_ar934x()) {
|
|
+ ath79_ip2_handler = ath79_default_ip2_handler;
|
|
+ ath79_ip3_handler = ar934x_ip3_handler;
|
|
++ } else if (soc_is_qca953x()) {
|
|
++ ath79_ip2_handler = ath79_default_ip2_handler;
|
|
++ ath79_ip3_handler = ath79_default_ip3_handler;
|
|
+ } else if (soc_is_qca955x()) {
|
|
+ ath79_ip2_handler = ath79_default_ip2_handler;
|
|
+ ath79_ip3_handler = ath79_default_ip3_handler;
|
|
+--- a/arch/mips/ath79/setup.c
|
|
++++ b/arch/mips/ath79/setup.c
|
|
+@@ -164,6 +164,12 @@ static void __init ath79_detect_sys_type
|
|
+ rev = id & AR934X_REV_ID_REVISION_MASK;
|
|
+ break;
|
|
+
|
|
++ case REV_ID_MAJOR_QCA9533:
|
|
++ ath79_soc = ATH79_SOC_QCA9533;
|
|
++ chip = "9533";
|
|
++ rev = id & AR944X_REV_ID_REVISION_MASK;
|
|
++ break;
|
|
++
|
|
+ case REV_ID_MAJOR_QCA9558:
|
|
+ ath79_soc = ATH79_SOC_QCA9558;
|
|
+ chip = "9558";
|
|
+@@ -176,7 +182,7 @@ static void __init ath79_detect_sys_type
|
|
+
|
|
+ ath79_soc_rev = rev;
|
|
+
|
|
+- if (soc_is_qca955x())
|
|
++ if (soc_is_qca953x() || soc_is_qca955x())
|
|
+ sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
|
|
+ chip, rev);
|
|
+ else
|
|
+--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
++++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
|
|
+@@ -106,6 +106,9 @@
|
|
+ #define AR934X_NFC_BASE 0x1b000200
|
|
+ #define AR934X_NFC_SIZE 0xb8
|
|
+
|
|
++#define QCA953X_WMAC_BASE (AR71XX_APB_BASE + 0x00100000)
|
|
++#define QCA953X_WMAC_SIZE 0x20000
|
|
++
|
|
+ #define QCA955X_PCI_MEM_BASE0 0x10000000
|
|
+ #define QCA955X_PCI_MEM_BASE1 0x12000000
|
|
+ #define QCA955X_PCI_MEM_SIZE 0x02000000
|
|
+@@ -280,6 +283,43 @@
|
|
+
|
|
+ #define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
|
|
+
|
|
++#define QCA953X_PLL_CPU_CONFIG_REG 0x00
|
|
++#define QCA953X_PLL_DDR_CONFIG_REG 0x04
|
|
++#define QCA953X_PLL_CLK_CTRL_REG 0x08
|
|
++#define QCA953X_PLL_ETH_XMII_CONTROL_REG 0x2c
|
|
++#define QCA953X_PLL_ETH_SGMII_CONTROL_REG 0x48
|
|
++
|
|
++#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
|
|
++#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
|
|
++#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
|
|
++#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
|
|
++#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
|
|
++#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
|
|
++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
|
|
++#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
|
|
++
|
|
++#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
|
|
++#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
|
|
++#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
|
|
++#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
|
|
++#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
|
|
++#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
|
|
++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
|
|
++#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
|
|
++
|
|
++#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
|
|
++#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
|
|
++#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
|
|
++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
|
|
++#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
|
|
++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
|
|
++#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
|
|
++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
|
|
++#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
|
|
++#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
|
|
++#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
|
|
++#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
|
|
++
|
|
+ #define QCA955X_PLL_CPU_CONFIG_REG 0x00
|
|
+ #define QCA955X_PLL_DDR_CONFIG_REG 0x04
|
|
+ #define QCA955X_PLL_CLK_CTRL_REG 0x08
|
|
+@@ -354,6 +394,10 @@
|
|
+ #define AR934X_RESET_REG_BOOTSTRAP 0xb0
|
|
+ #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS 0xac
|
|
+
|
|
++#define QCA953X_RESET_REG_RESET_MODULE 0x1c
|
|
++#define QCA953X_RESET_REG_BOOTSTRAP 0xb0
|
|
++#define QCA953X_RESET_REG_EXT_INT_STATUS 0xac
|
|
++
|
|
+ #define QCA955X_RESET_REG_BOOTSTRAP 0xb0
|
|
+ #define QCA955X_RESET_REG_EXT_INT_STATUS 0xac
|
|
+
|
|
+@@ -468,6 +512,8 @@
|
|
+ #define AR934X_BOOTSTRAP_SDRAM_DISABLED BIT(1)
|
|
+ #define AR934X_BOOTSTRAP_DDR1 BIT(0)
|
|
+
|
|
++#define QCA953X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
|
++
|
|
+ #define QCA955X_BOOTSTRAP_REF_CLK_40 BIT(4)
|
|
+
|
|
+ #define AR934X_PCIE_WMAC_INT_WMAC_MISC BIT(0)
|
|
+@@ -530,6 +576,7 @@
|
|
+ #define REV_ID_MAJOR_AR9341 0x0120
|
|
+ #define REV_ID_MAJOR_AR9342 0x1120
|
|
+ #define REV_ID_MAJOR_AR9344 0x2120
|
|
++#define REV_ID_MAJOR_QCA9533 0x0140
|
|
+ #define REV_ID_MAJOR_QCA9558 0x1130
|
|
+
|
|
+ #define AR71XX_REV_ID_MINOR_MASK 0x3
|
|
+@@ -603,6 +650,7 @@
|
|
+ #define AR913X_GPIO_COUNT 22
|
|
+ #define AR933X_GPIO_COUNT 30
|
|
+ #define AR934X_GPIO_COUNT 23
|
|
++#define QCA953X_GPIO_COUNT 24 /* (?) */
|
|
+ #define QCA955X_GPIO_COUNT 24
|
|
+
|
|
+ /*
|
|
+--- a/arch/mips/include/asm/mach-ath79/ath79.h
|
|
++++ b/arch/mips/include/asm/mach-ath79/ath79.h
|
|
+@@ -32,6 +32,7 @@ enum ath79_soc_type {
|
|
+ ATH79_SOC_AR9341,
|
|
+ ATH79_SOC_AR9342,
|
|
+ ATH79_SOC_AR9344,
|
|
++ ATH79_SOC_QCA9533,
|
|
+ ATH79_SOC_QCA9558,
|
|
+ };
|
|
+
|
|
+@@ -99,6 +100,16 @@ static inline int soc_is_ar934x(void)
|
|
+ return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
|
|
+ }
|
|
+
|
|
++static inline int soc_is_qca9533(void)
|
|
++{
|
|
++ return ath79_soc == ATH79_SOC_QCA9533;
|
|
++}
|
|
++
|
|
++static inline int soc_is_qca953x(void)
|
|
++{
|
|
++ return soc_is_qca9533();
|
|
++}
|
|
++
|
|
+ static inline int soc_is_qca9558(void)
|
|
+ {
|
|
+ return ath79_soc == ATH79_SOC_QCA9558;
|